/** @file sys_main.c 
*   @brief Application main file
*   @date 25.July.2013
*   @version 03.06.00
*
*   This file contains an empty main function,
*   which can be used for the application.
*/

/* (c) Texas Instruments 2009-2013, All rights reserved. */

/* USER CODE BEGIN (0) */
#include "sci.h"
#include "sys_dma.h"
/* USER CODE END */

/* Include Files */

#include "sys_common.h"
#include "system.h"

/* USER CODE BEGIN (1) */
#define D_SIZE 32
uint32 TX_DATA[D_SIZE];     /* DMA source buffer */
g_dmaCTRL g_dmaCTRLPKT;
/* USER CODE END */

/** @fn void main(void)
*   @brief Application main function
*   @note This function is empty by default.
*
*   This function is called after startup.
*   The user can use this function to implement the application.
*/

/* USER CODE BEGIN (2) */
void load_data(void)
{
	int i;
	for (i=0;i<D_SIZE;i++)
	{

		TX_DATA[i] = 0xE1+i;
	}
}

/* USER CODE END */

void main(void)
{
	/* USER CODE BEGIN (3) */
		/* - initializing mibspi - enabling tg 0 */
		sciInit();
		load_data();
		/* - DMA Configuration */

		/* Enable DMA */
		dmaEnable();

		/* assigning dma request: channel-0 with request line - 1  - TX*/
	    /* DMA Request 29 is for LIN ( SCI2) Transmit */
	    /* Refer Data sheet - Default DMA Request Map section */
		dmaReqAssign(DMA_CH0,29);
	    	/* - configuring dma control packets   */
	    	g_dmaCTRLPKT.SADD      = (uint32)(&TX_DATA);  /* source address             */
	    	g_dmaCTRLPKT.DADD      = (uint32)(&scilinREG->TD);       /* destination  address       */
	    	g_dmaCTRLPKT.CHCTRL    = 0;                 /* channel control            */
	    	g_dmaCTRLPKT.FRCNT      = D_SIZE;                 /* frame count                */
	    	g_dmaCTRLPKT.ELCNT     =1 ;            /* element count              */
	    	g_dmaCTRLPKT.ELDOFFSET = 0;      /* element destination offset - is required?      */
	    	g_dmaCTRLPKT.ELSOFFSET = 0;      /* element source offset   - is required?           */
	    	g_dmaCTRLPKT.FRDOFFSET = 0;      /* frame detination offset  - is required?          */
	    	g_dmaCTRLPKT.FRSOFFSET = 0;      /* frame source offset   - is required?             */
	    	g_dmaCTRLPKT.PORTASGN  = 4;                 /* port b                     */
	    	g_dmaCTRLPKT.RDSIZE    = ACCESS_32_BIT;       /* read size                  */
	    	g_dmaCTRLPKT.WRSIZE    = ACCESS_32_BIT;        /* write size                 */
	    	g_dmaCTRLPKT.TTYPE     = FRAME_TRANSFER ;   /* transfer type              */
	    	g_dmaCTRLPKT.ADDMODERD = ADDR_INC1;         /* address mode read          */
	    	g_dmaCTRLPKT.ADDMODEWR = ADDR_FIXED;        /* address mode write         */
	    	g_dmaCTRLPKT.AUTOINIT  = AUTOINIT_ON;       /* autoinit  (loop)           */
	    	dmaSetCtrlPacket(DMA_CH0,g_dmaCTRLPKT);
		/* - setting dma control packets for transmit */
	    dmaSetCtrlPacket(DMA_CH0,g_dmaCTRLPKT);

	    /* - setting the dma channel to trigger on h/w request */
	    dmaSetChEnable(DMA_CH0, DMA_HW);

		/* Enable TX DMA */
		scilinREG->SETINT = (1 << 16U);



	    while(1); /* loop forever */


	/* USER CODE END */
}
/* USER CODE BEGIN (4) */
/* USER CODE END */
