This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

关于DM642语音处理问题(AIC23B、MCASP)

一开始产生单频声音是好使的,后来加上延时就不好使了。本来并没有延时,只是我用来调试程序的(延时部分可以算作算法的部分),但此时,就没有声音发出了。使用的是奇想达DM642的板子。主函数如下:

for(;;)
	{
		
  
		  
		if(MCASP_FGETH(QXDdm642codec,RSTAT,RDATA))
		{
			codecdata[0] = MCASP_RGETH(QXDdm642codec,RBUF1);

			MCASP_RSETH(QXDdm642codec,XBUF0,codecdata[0]);
			
			codecdata[1] = MCASP_RGETH(QXDdm642codec,RBUF3);
			MCASP_RSETH(QXDdm642codec,XBUF2,codecdata[1]);

//			for(b=0;b<1000;b++) {}   //这一段代码加上后就没有声音发出了,当b=100或者更小时,有声音发出
			
			codecdata[2] = MCASP_RGETH(QXDdm642codec,RBUF5);		
			MCASP_RSETH(QXDdm642codec,XBUF4,15000*sin(0.1*PI*n));	
			
			codecdata[3] = MCASP_RGETH(QXDdm642codec,RBUF7);
			MCASP_RSETH(QXDdm642codec,XBUF6,codecdata[3]);	
			
			n++;
			if(n>20)
			n=0;	
		
		}
		else
		{
			    asm(" nop");
		}

其中,AIC23B的配置如下:

#define QXDDM642_AIC23_DEFAULTCONFIG { \
    0x0017, /* Set-Up Reg 0       左线输入通道音量控制 Left line input channel volume control */  \
            /* LRS     0          simultaneous left/right volume: disabled */\
            /* LIM     0          left line input mute: disabled */          \
            /* XX      00         reserved */                                \
            /* LIV     10111      left line input volume: 0 dB */            \
                                                                             \
    0x0017, /* Set-Up Reg 1       右线输入通道音量控制 Right line input channel volume control */ \
            /* RLS     0          simultaneous right/left volume: disabled */\
            /* RIM     0          right line input mute: disabled */         \
            /* XX      00         reserved */                                \
            /* RIV     10111      right line input volume: 0 dB */           \
                                                                             \
    0x01f9, /* Set-Up Reg 2       左通道耳机音量控制 Left channel headphone volume control */   \
            /* LRS     1          simultaneous left/right volume: enabled */ \
            /* LZC     1          left channel zero-cross detect: enabled 过零检测*/ \
            /* LHV     1111001    left headphone volume: 0 dB */             \
                                                                             \
    0x01f9, /* Set-Up Reg 3       右通道耳机音量控制 Right channel headphone volume control */  \
            /* RLS     1          simultaneous right/left volume: enabled */ \
            /* RZC     1          right channel zero-cross detect: enabled */\
            /* RHV     1111001    right headphone volume: 0 dB */            \
                                                                             \
    0x0011, /* 0x0011  0x0015   Set-Up Reg 4  模拟音频路径控制    Analog audio path control */           \
            /* X       0          reserved */                                \
            /* STA     00         sidetone attenuation: -6 dB */             \
            /* STE     0          sidetone: disabled */                      \
            /* DAC     1          DAC: selected */                           \
            /* BYP     0          旁路 bypass: off */                             \
            /* INSEL   0          ADC选择输入 线输入,为何不是MIC输入???   input select for ADC: line    */              \
            /* MICM    0          microphone mute: disabled */               \
            /* MICB    1          麦克风增强 microphone boost: enabled C5509板子上程序没有增强*/               \
                                                                             \
    0x0000, /* Set-Up Reg 5       数字音频路径控制 Digital audio path control */              \
            /* XXXXX   00000      reserved */                                \
            /* DACM    0          DAC soft mute: disabled */                 \
            /* DEEMP   00         deemphasis control: disabled */            \
            /* ADCHP   0          ADC high-pass filter: disabled */          \
                                                                             \
    0x0000, /* Set-Up Reg 6       断电控制  Power down control */                      \
            /* X       0          reserved */                                \
            /* OFF     0          device power: on (i.e. not off) */         \
            /* CLK     0          clock: on */                               \
            /* OSC     0          oscillator: on */                          \
            /* OUT     0          outputs: on */                             \
            /* DAC     0          DAC: on */                                 \
            /* ADC     0          ADC: on */                                 \
            /* MIC     0          microphone: on */                          \
            /* LINE    0          line input: on */                          \
                                                                             \
    0x0053, /* Set-Up Reg 7       数字音频接口格式 Digital audio interface format */          \
            /* XX      00         reserved */                                \
            /* MS      1          主模式 master/slave mode: master */               \
            /* LRSWAP  0          DAC的左/右互换 DAC left/right swap: disabled */           \
            /* LRP     0          DAC lrp: MSB on 1st BCLK */                \
            /* IWL     00         输入位长度:16位。input bit length: 16 bit */                \
            /* FOR     11         数据格式:DSP格式 data format: DSP format */                 \
                                                                             \
    0x000e, /* Set-Up Reg 8       采样率控制 Sample rate control     //修改 原先为0002,ADC\DAC均为8Khz normal模式 */      \
            /* X       0          reserved */                                \
            /* CLKOUT  0          时钟输出分频:1  clock output divider: 1 MCLK */        \
            /* CLKIN   0          时钟输入分频:1 clock input divider: 1 (MCLK) */           \
            /* SR,BOSR 00110      sampling rate: ADC  8 kHz DAC  8 kHz */  \
            /* USB/N   0          clock mode select (USB/nor  mal): normal */     \
                                                                             \
    0x0001  /* Set-Up Reg 9       数字接口激活 Digital interface activation */            \
            /* XX..X   00000000   reserved */                                \
            /* ACT     1          active */                                  \
}

主程序中有:

	/*AIC23B的初始化*/
	hQXDdm642i2c = I2C_open(I2C_PORT0,I2C_OPEN_RESET);
	I2C_config(hQXDdm642i2c,&QXDDM642IIC_Config);
	/*配置第一路到第四路音频输入*/
	/*第一通路AIC23工作在主模式*/
//	codecstate.regs[QXDDM642_AIC23_DIGIF] = 0x13; 

	dm642aic23handle0 = EVMDM642_AIC23_open(hQXDdm642i2c,0,&codecstate);

	codecstate.regs[QXDDM642_AIC23_DIGIF] = 0x13;	
		/*其它三路工作在从模式*/
	dm642aic23handle1 = EVMDM642_AIC23_open(hQXDdm642i2c,1,&codecstate);
	dm642aic23handle2 = EVMDM642_AIC23_open(hQXDdm642i2c,2,&codecstate);
//	dm642aic23handle3 = EVMDM642_AIC23_open(hQXDdm642i2c,3,&codecstate);

MCASP的配置如下:

	/*MCASP的初始化*/
	QXDdm642codec = QXDDM642_AIC23_openCodec();

MCASP_ConfigGbl mcaspCfgDataGbl = {
    0x00000000, // PFUNC -     All pins as McASP ,所有的管脚均为McAPS功能
    0x00000055, //* PDIR  -     0,2,4,6为input,1,3,5,7为XMT DATA output, 其它的为输入 
    0x00000000, //* DITCTL -    DIT mode disable ,使用TDM mode or burst mode.
    0x00000000, //* DLBCTL -    Loopback disabled */
    0x00000000  //* AMUTE  -    Never drive AMUTE */
};

MCASP_ConfigRcv mcaspCfgDataRcv = {
    0xffffffff, //* RMASK -     Use all 32 bits,左声道与右声道各16位 
    0x000180f8, //* RFMT -      MSB first, 32-bit slots,0-pad,CPU bus, 0 bit delay,数据格式 
    0x00000200, //* AFSRCTL -   4-slots TDM, single bit frame sync, ext FS 帧同步的格式,修改过,原先为200
    0x00000080, /* ACLKRCTL -  时钟上升沿有效, 时钟不分频, 外部时钟模式from ACLKR pin. */
    0x00000000, //* AHCLKRCTL - External HCLK  外部接收高频时钟来自AHCLKR pin. */
    0x0000000f, /* RTDM -      Slots 1,3,5,7 are active */
    0x00000000, /* RINTCTL -   关闭所有中断 No interrupts */
    0x00000000  /* RCLKCHK -   Not used */ 
};

MCASP_ConfigXmt mcaspCfgDataXmt = {
    0xffffffff, /* XMASK -     Use all 32 bits,左声道与右声道各16位 */
    0x000180f8, /* XFMT -      MSB first, 32-bit slots, CPU bus, 0 bit delay */
    0x00000200, /* AFSXCTL -   burst, single bit frame sync, ext FS 4 slot TDM*/
    0x00000080, /* ACLKXCTL -  Sample on falling CLK, divide by 1, ext CLK ,发送与接收同步*/
    0x00000000, /* AHCLKXCTL - External HCLK */
    0x00000005, /* XTDM -      0,2,4,6 enable*/
    0x00000000, /* XINTCTL -   No interrupts */
    0x00000000  /* XCLKCHK -   Not used */
};

MCASP_ConfigSrctl mcaspCfgDataSrctl = {
    0x00000005, /* SRCTL0 -    Receive, active high   101发送  110接收 */
    0x00000006, /* SRCTL1 -    Transmit, active high*/
    0x00000005, /* SRCTL2 -    Receive, active high */
    0x00000006, /* SRCTL3 -    Transmit, active high */
    0x00000005, /* SRCTL4 -    Receive, active high */
    0x00000006, /* SRCTL5 -    Transmit, active high*/
    0x00000005, /* SRCTL6 -    Receive, active high */
    0x00000006  /* SRCTL7 -    Transmit, active high */
};

MCASP_Config mcaspCfgData = {
    &mcaspCfgDataGbl,
    &mcaspCfgDataRcv,
    &mcaspCfgDataXmt,
    &mcaspCfgDataSrctl
};

/***************************************************************************/
/*  ======== EVMDM642_AIC23_openCodec ========							   */
/*  Open the codec and return a codec handle							   */
/***************************************************************************/
MCASP_Handle QXDDM642_AIC23_openCodec()
{
    Uint32 gblctl;
    /* AIC23 handles,定义McASP的句柄*/
    MCASP_Handle QXDDM642_AIC23_hMcASP;
    /* Open and configure the McASP*/
    QXDDM642_AIC23_hMcASP = MCASP_open(MCASP_DEV0, MCASP_OPEN_RESET);
    /*配制McASP */
    MCASP_config(QXDDM642_AIC23_hMcASP, &mcaspCfgData);
    
    /* Clear transmit and receive status ,清除发送与接收状态*/
    MCASP_RSETH(QXDDM642_AIC23_hMcASP, RSTAT, 0xffff);
    MCASP_RSETH(QXDDM642_AIC23_hMcASP, XSTAT, 0xffff);

    /* Clear GBLCTL,将所有的单元复位 */
    gblctl = 0;
    MCASP_RSETH(QXDDM642_AIC23_hMcASP, GBLCTL, gblctl);
    gblctl = 0x404;
    /*使能发送与接收的串行寄存器*/    
    MCASP_RSETH(QXDDM642_AIC23_hMcASP, GBLCTL, 0x404);              
    /* Enable transmit/receive state machines */
    MCASP_RSETH(QXDDM642_AIC23_hMcASP, XBUF0, 0);
    MCASP_RSETH(QXDDM642_AIC23_hMcASP, XBUF2, 0);
    MCASP_RSETH(QXDDM642_AIC23_hMcASP, XBUF4, 0);
    MCASP_RSETH(QXDDM642_AIC23_hMcASP, XBUF6, 0);
    gblctl = 0x0c0c;
    MCASP_RSETH(QXDDM642_AIC23_hMcASP, GBLCTL, gblctl);

    return QXDDM642_AIC23_hMcASP;
}

实在不知道问题出在哪里,怎么解决。求各位帮忙,谢谢!