求助。BQ76930ALERT引脚使用问题,急急急

求助。BQ76930ALERT引脚使用问题,急急急

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  • 秀才40分

    最近在做BQ76930,用的飞思卡尔的MCU,在测试时发现ALERT引脚上一直会有中断产生,所以借用了这个中断来读取有效电流,正常情况下,并没有发现啥问题,每次进中断判断了CC_READY位是否有效后读取有效电流计算容量,但当我把MCU休眠过后,再次唤醒的时候问题出现了,在我仅仅将CC_READY位在唤醒后清零时,过流保护不会检测负载就直接恢复且不能正常进入休眠,当我在此基础上读取一下电流后,再过流后,就有了断开负载恢复这一功能,同时MCU也能正常进入低功耗和退出低功耗,相当于我读取电流后进入了ALERT中断或者是使能了ALERT中断,现在还没弄明白为啥要这样操作或者这样操作的理由又是啥,急急急,有相关大拿看到的话帮忙解决一下

  • 秀才330分

    你好,最近也在研究BQ76930,Alert不是警报引脚吗,怎么会一直有中断,另外CC值为什么你要用ALERT去触发读取,CC值的读取可以放在休眠定时器去执行啊,一直读取,累计计算容量。

  • 秀才40分

    您好,我想通过ALERT这个信号来进一步判断电流是否为有效值,即CC_READY位是否为1。当CC-READY位为1时才能判定此电流值为有效值,一直查询的方式我还没有验证可行性,如果查询的话可能需要在250MS内读取多次CC_READY位,来判断该位的状态

  • 秀才40分

    您那边方便的话可以留一个QQ或者微信方便交流,15620616883,这是我微信号

  • 秀才330分

    你好,我的样板要过段时间才能拿到,所以现在也只是研究Datasheet和搭建软件。我刚刚仔细看datasheet, ALERT确实有CC更新中断功能,但不止这一个功能,同时还具有fault evevt功能。所以是不是fault evevt影响。另,你的MCU是怎样区分这两种中断的。

    The bq769x0 provides two low-side FET drivers, charge (CHG) and discharge (DSG), which may be used
    to directly manipulate low-side power NCH FETs, or as signals that control an external circuit that enables
    high-side PCH or NCH FETs. A dedicated ALERT input/output pin serves as an interrupt signal to the host
    microcontroller, quickly informing the microcontroller of an updated status in the AFE. This may include a
    fault event or that a coulomb counter sample is available for reading. An available ALERT pin may also be
    driven externally by a secondary protector to provide a redundant means of disabling the CHG and DSG
    signals and higher system visibility.

    The Protection subsystem provides a baseline or secondary level of hardware protections to better
    support a battery pack’s FMEA requirements in the event of a loss of host control or simply if a host is
    unable to respond to a certain fault event in time. Integrated protections include pack-level faults such
    as OV, UV, OCD, SCD, detection of an external secondary protector fault, and internal logic
    “watchdog”-style device fault (XREADY). Protection events will trigger toggling of the ALERT pin, as
    well as automatic disabling of the DSG and/or CHG FET driver (depending on the fault). Recovery
    from a fault event must be handled by the host microcontrolle

    In ALWAYS ON mode, the CC runs at 100%, gathering a fresh reading every 250 ms. The conclusion
    of each reading sets the CC_READY bit, which toggles the ALERT pin high to inform the
    microcontroller that a new reading is available. To enable Always On mode, set [CC_EN] = 1.

    Overcurrent in Discharge (OCD) and Short Circuit in Discharge (SCD) are implemented using sampled
    analog comparators that run at 32 kHz, and that continuously monitor the voltage across (SRP–SRN)
    while the device is in NORMAL mode. Upon detection of a voltage that exceeds the programmed OCD or
    SCD threshold, a counter begins to count up to a programmed delay setting. If the counter reaches its
    target value, the SYS_STAT register is updated to indicate the fault condition, the FET state(s) are
    updated as shown in
    表7-1, and the ALERT pin is driven high to interrupt the host.

  • 秀才40分

    读取到ALERT中断后读取0X00寄存器状态判断是CC_READY位是否为1,为1,则表明电流有效读取电流,读取到其他状态的时候会根据状态做相应的动作