急急急！！！这两天我用430g2452的USI模块的I2C模式来跟bq24195进行通信，读取bq24195的时候读取回来的数据都是0xff，我怀疑我自己写的读取代码有问题然后我就查看了一下读取时序，发现发送每一字节数据之后等待从机回应ACK的过程中SCL是高电平状态（空闲状态），正常情况下不是被从机拉低的么？这是软件问题还是硬件上存在问题呢。一下我把I2C配置代码贴出，请大家帮忙一下....
void I2c_Master_2452(void) //配置I2C模块
{
USICTL0 = USIPE6+USIPE7+USIMST+USISWRST; // Port & USI mode setup
USICTL1 = USII2C+USIIE; // Enable I2C mode & USI interrupt
USICKCTL = USIDIV_3+USISSEL_2+USICKPL; // Setup USI clocks: SCL = SMCLK/8 (~125kHz)
USICNT |= USIIFGCC; // Disable automatic clear control
USICTL0 &= ~USISWRST; // Enable USI
USICTL1 &= ~USIIFG; // Clear pending flag
}
这个配置是TI官网上的例程。
下面是我中断服务程序里面读取寄存器的代码
{
switch(I2C_State)
{
case 0: // Generate Start Condition & send address to slave
USISRL = 0x00; // set MSB of the shiftregister to 0
USICTL0 |= USIGE+USIOE; //置位USIGE、USIOE
USICTL0 &= ~USIGE; //清除USIGE
USISRL = 0X0D6; // ... and transmit address, R/W = 0
USICNT = (USICNT & 0xE0) + 0x08; // Bit counter = 8, TX Address
I2C_State = 2; // Go to next state: receive address (N)Ack
break;
case 2: // Receive Address Ack/Nack bit
USICTL0 &= ~USIOE; // SDA = input
USICNT |= 0x01; // Bit counter = 1, receive (N)Ack bit
I2C_State = 4; // Go to next state: check (N)Ack
break;
case 4: // Process Address Ack/Nack & handle data TX
USICTL0 |= USIOE; // SDA = output
if (USISRL & 0x01) // If Nack received...
{ // Send stop...
USISRL = 0x00;
USICNT |= 0x01; // Bit counter = 1, SCL high, SDA low
I2C_State = 18; // Go to next state: generate Stop
}
else
{ // Ack received, TX data to slave...
USISRL = RegAddr; // 发送要访问的寄存器地址
USICNT |= 0x08; // Bit counter = 8, start TX
I2C_State = 6; // Go to next state: receive data (N)Ack
}
break;
case 6: // Receive Address Ack/Nack bit
USICTL0 &= ~USIOE; // SDA = input
USICNT |= 0x01; // Bit counter = 1, receive (N)Ack bit
I2C_State = 8; // Go to next state: check (N)Ack
break;
case 8: // Process Address Ack/Nack & handle data TX
USICTL0 |= USIOE; // SDA = output
if (USISRL & 0x01) // If Nack received...
{ // Send stop...
USISRL = 0x00;
USICNT |= 0x01; // Bit counter = 1, SCL high, SDA low
I2C_State = 18; // Go to next state: generate Stop
}
else
{
// 产生开始条件并发送从机地址
// Delay_1ms(1);
USISRL = 0x00; // set MSB of the shiftregister to 0
USICTL0 |= USIGE+USIOE; //置位USIGE、USIOE
USICTL0 &= ~USIGE; //清除USIGE
USISRL = 0x0D7; // ... and transmit address, R/W = 0
USICNT = (USICNT & 0xE0) + 0x08; // Bit counter = 8, TX Address
I2C_State = 10; // Go to next state: receive address (N)Ack
}
break;
case 10: // Receive Data Ack/Nack bit
USICTL0 &= ~USIOE; // SDA = input
USICNT |= 0x01; // Bit counter = 1, receive (N)Ack bit
I2C_State = 12; // Go to next state: check (N)Ack
break;
case 12: // Process Data Ack/Nack & send Stop
USICTL0 |= USIOE;
if (USISRL & 0x01) // If Nack received...
{ // Send stop...
USISRL = 0x00;
USICNT |= 0x01; // Bit counter = 1, SCL high, SDA low
I2C_State = 18; // Go to next state: generate Stop
}
else // Ack received
{ //接收bq24195数据
USICTL0 &= ~USIOE; // SDA = input
USICNT |= 0x08; // Bit counter = 1, receive (N)Ack bit
I2C_State = 14; // Go to next state: check (N)Ack
}
break;
case 14: // Process bq24195发来的数据 and Transmit Data Nack bit
ReadData = USISRL;
USISRL = 0x01;
USICTL0 |= USIOE; // SDA = output
USICNT |= 0x01; // Bit counter = 1, receive (N)Ack bit
I2C_State = 16; // Go to next state: check (N)Ack
break;
case 16://Send Stop ...
USISRL = 0x00;
USICNT |= 0x01; // Bit counter = 1, SCL high, SDA low
I2C_State = 18; // Go to next state: generate Stop
break;
case 18: // Generate Stop Condition
USISRL = 0x0FF; // USISRL = 1 to release SDA
USICTL0 |= USIGE; // Transparent latch enabled
USICTL0 &= ~(USIGE+USIOE);// Latch/SDA output disabled
I2C_State = 0; // Reset state machine for next transmission
LPM0_EXIT; // Exit active for next transfer
break;
}
USICTL1 &= ~USIIFG; // Clear pending flag
}
