We use in one of our product the THS 788 chip (from TI) and we are encountering some trouble with it.
In our setup we connect to Sync Input A and EventA two periodic signals slightly delayed by 1 ns.
Then we vary their common frequency.
We observe the following behavior when reading the internal ChannelA result register:
- The results are correct when the common frequency is lower than 8MHz. (we can read a correct delay of 1 ns)
- For frequencies between 9MHz to 25MHz, we observe 3 different values of the delay (1 ns, 1ns + period of signal, 1 ns - period)
- For higher frequencies (60MHz to 80MHz) we observe many values, which seem related by multiple of the signal period. (1 ns - 27 period, 1 ns - 28 period. etc.)
Could you have additional information regarding this behavior.
- The manual mentions negative timestamps when start occurs just after a stop but can the delays be larger than the time window between two starts ?
In addition we are using the high speed serial interface to read data from our FPGA which is configured in 8 bit mode.
- The documentation mentions the last bit as the sign bit which we do not observe. Do we have a way to program it as it or are we doing something wrong ?
The THS788 is configured as follow: (non specified registers are set their initial values)
- Control register values:
- 0x80 -> 0xA600
- RCLK_EN = '1', Result Clock Enabled
- Sync_IP_En = '1', Enables the sync channel
- OT_En = '1', Enables the overtemperature alarm circuits
- RCLK_Sel = "10", Result-Interface Clock = 300MHz
- RLenght = "000" -> Result transfer format = 8 bits
- Control register values:
- 0x81 -> 0x0002
- CHA_IP_EN= "1",
- EN_CHA = "1"
- DDR 0x00 CHA Control Register -> DATA 0x0003 -> CHA_IP_EN(1), EN_CHA(1
- 0x00 -> 0x0003
- CHA_IP_EN = "1",
- EN_CHA = "1"