把C6713的McBSP配置成SPI主模式，运行程序后在CLKX管脚没有时钟，DX管脚没有数据输出，FSX管脚也没有信号输出。McBSP配置如下：
MCBSP_Config Config_Spi_Master = {
MCBSP_SPCR_RMK(
MCBSP_SPCR_FREE_DEFAULT,
MCBSP_SPCR_SOFT_DEFAULT,
MCBSP_SPCR_FRST_YES,
MCBSP_SPCR_GRST_YES,
MCBSP_SPCR_XINTM_XRDY,
MCBSP_SPCR_XSYNCERR_NO,
MCBSP_SPCR_XRST_YES,
MCBSP_SPCR_DLB_OFF,
MCBSP_SPCR_RJUST_RZF,
MCBSP_SPCR_CLKSTP_NODELAY, //Clock phase: 10
MCBSP_SPCR_DXENA_OFF,
MCBSP_SPCR_RINTM_RRDY,
MCBSP_SPCR_RSYNCERR_NO,
MCBSP_SPCR_RRST_YES
),
MCBSP_RCR_RMK(
MCBSP_RCR_RPHASE_SINGLE, //Must single phase in spi mode
MCBSP_RCR_RFRLEN2_OF(0),
MCBSP_RCR_RWDLEN2_8BIT,
MCBSP_RCR_RCOMPAND_MSB,
MCBSP_RCR_RFIG_NO,
MCBSP_RCR_RDATDLY_1BIT, //Master mode: RDATDLY and XDATDLY must be 1
MCBSP_RCR_RFRLEN1_OF(0), //Must be 1 frame in spi mode
MCBSP_RCR_RWDLEN1_32BIT,
MCBSP_RCR_RWDREVRS_DISABLE
),
MCBSP_XCR_RMK(
MCBSP_XCR_XPHASE_SINGLE, //Must single phase in spi mode
MCBSP_XCR_XFRLEN2_OF(0),
MCBSP_XCR_XWDLEN2_8BIT,
MCBSP_XCR_XCOMPAND_MSB,
MCBSP_XCR_XFIG_NO,
MCBSP_XCR_XDATDLY_1BIT, //Master mode: RDATDLY and XDATDLY must be 1
MCBSP_XCR_XFRLEN1_OF(0), //Must 1 frame in spi mode
MCBSP_XCR_XWDLEN1_32BIT,
MCBSP_XCR_XWDREVRS_DISABLE
),
MCBSP_SRGR_RMK(
MCBSP_SRGR_GSYNC_FREE,
MCBSP_SRGR_CLKSP_RISING,
MCBSP_SRGR_CLKSM_INTERNAL,
MCBSP_SRGR_FSGM_DXR2XSR, // Every DXR to XSR copy generates FSX
MCBSP_SRGR_FPER_OF(0),
MCBSP_SRGR_FWID_OF(0),
MCBSP_SRGR_CLKGDV_OF(9) //CLKG = CPU/2/CLKGDV
),
MCBSP_MCR_DEFAULT,
MCBSP_RCER_DEFAULT,
MCBSP_XCER_DEFAULT,
MCBSP_PCR_RMK(
MCBSP_PCR_XIOEN_SP,
MCBSP_PCR_RIOEN_SP,
MCBSP_PCR_FSXM_INTERNAL, //Must be 1 in master mode
MCBSP_PCR_FSRM_EXTERNAL,
MCBSP_PCR_CLKXM_OUTPUT, //Must be 1 in master mode, CLKG generates CLKX
MCBSP_PCR_CLKRM_INPUT,
MCBSP_PCR_CLKSSTAT_0,
MCBSP_PCR_DXSTAT_0,
MCBSP_PCR_FSXP_ACTIVELOW, //Chip selected active low(master mode)
MCBSP_PCR_FSRP_ACTIVELOW,
MCBSP_PCR_CLKXP_FALLING, //Clock polarity: 1
MCBSP_PCR_CLKRP_FALLING
)
};
主函数
void main(void)
{
CSL_init();
hMcbsp_Master = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET);
MCBSP_config(hMcbsp_Master, &Config_Spi_Master);
/*Start McBSP and timer1*/
MCBSP_start(hMcbsp_Master, MCBSP_RCV_START | MCBSP_XMIT_START | MCBSP_SRGR_START
| MCBSP_SRGR_FRAMESYNC, 0x00003000);
while(1)
{
MCBSP_write(hMcbsp_Master, 0xaaaaaaaa);
while(!(MCBSP_xrdy(hMcbsp_Master)));
}
}
