C6455 Timer内部时钟源时钟频率是多少？

PLL1的Divder3是固定值1/6，不能修改的，所以没有Divider3寄存器。在数据手册第134页上有说明。
 

The divider ratio bits of dividers D2 and D3 are fixed at ÷3 and ÷6, respectively. The divider ratio bits of
dividers D4 and D5 are programmable through the PLL controller divider registers PLLDIV4 and PLLDIV5,
respectively.

Yuchen Wang1 说：

在配置C6455 Timer时钟源为Internal clock，查看C6455数据手册时有写到

SYSCLK3 clocks the PCI, HPI, UTOPIA, McBSP, GPIO, TIMER, and I2C peripherals,

则Internal clock是由SYSCLK3 clocks提供的，那么Timer的Internal clock是CPU Clock/3嘛？

请指教