现在想用6455与FPGA通信,使用AECLKOUT,AEA15管脚为高电平,看datasheet应该是以SYSCLK4为时钟源,可是挂上仿真器后,显示时钟源为SYSCLK3
而且AECLKOUT管脚无时钟输出,但是GP[1]的管脚有正常的时钟输出。想要AECLKOUT输出时钟还需要别的配置吗?PLL1已经为使能状态
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现在想用6455与FPGA通信,使用AECLKOUT,AEA15管脚为高电平,看datasheet应该是以SYSCLK4为时钟源,可是挂上仿真器后,显示时钟源为SYSCLK3
而且AECLKOUT管脚无时钟输出,但是GP[1]的管脚有正常的时钟输出。想要AECLKOUT输出时钟还需要别的配置吗?PLL1已经为使能状态