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k2 GE

按照k2_STK中的GE千兆网调试,完成了MAC,SGMII,SERDES的内部环回。

在执行DSP0->DSP1以及Extrenal_FIFO_loopback时:输出条件如下:(自己的板子,没有使用物理芯片,使用FORCE LINK进行网络通信)

Initialize DSP main clock = 156.25MHz/3x23 = 1197MHz
Initialize PASS clock = 156.25MHzx168/25 = 1050.000MHz
DDR3A initialization
Initialize DDR data rate = 156.250x32/5= 1000.0 MTS
Enable Exception handling...
GE 1000M fullduplex two DSPs test (DSP0 -> DSP1)...

此时:卡在了Wait_PHY_link的函数里。(使用EVM板也是卡在这个函数里)

问题1:这是什么情况?是环回连接没接好?还是代码修改不对?

问题2:是否有关于外部环回的文档。关于外部环回的发与收端口是那个?

  • Hi, 您好!

    1. 你的板子,没有PHY, 所以不需要初始化PHY,不需要看PHY的状态,删除:

        Wait_PHY_link();

         K2_MDIO_Init(ge_cfg->mdio_cfg);

    2. EVM板

        2.1  假如你是用两块EVM板连接

              一块设置为ETHERNET_AUTO_NEGOTIAT_MASTER;运行在核0;

               一块设置为ETHERNET_AUTO_NEGOTIAT_SLAVE;运行在核1;

        2.2   假如你是用EVM板与PC或其他网络相连

               设置为ETHERNET_AUTO_NEGOTIAT_SLAVE;运行在核1;

     

  • 你好,我用的是两块EVM板,我照着你说的

    一块设置为ETHERNET_AUTO_NEGOTIAT_MASTER;运行在核0;

     一块设置为ETHERNET_AUTO_NEGOTIAT_SLAVE;运行在核1;

    设置了,显示的结果如下:

    JTAG ID= 0x1009e02f. This is C6678/TCI6608 device, version variant = 1.
    DEVSTAT= 0x00003001. little endian, No boot or EMIF16(NOR FLASH) or UART boot, PLL configuration implies the input clock for core is 312.5MHz.
    SmartReflex VID= 63, required core voltage= 1.104V.
    Die ID= 0x1201300d, 0x0403e8ae, 0x00000000, 0x46b00001
    Device speed grade = 1200MHz.
    Enable Exception handling...
    Initialize DSP main clock = 100.00MHz/1x10 = 1000MHz
    Initialize PASS PLL clock = 100.00MHz/2x21 = 1050.000MHz
    Initialize DDR speed = 66.67MHzx/1x20 = 1333.333MTS
    GE auto negotiation (master) two DSPs test (DSP0 -> DSP1)...
    JTAG ID= 0x1009e02f. This is C6678/TCI6608 device, version variant = 1.
    DEVSTAT= 0x00003001. little endian, No boot or EMIF16(NOR FLASH) or UART boot, PLL configuration implies the input clock for core is 312.5MHz.
    SmartReflex VID= 63, required core voltage= 1.104V.
    Die ID= 0x1201300d, 0x0403e8ae, 0x00000000, 0x46b00001
    Device speed grade = 1200MHz.
    Enable Exception handling...
    Initialize DSP main clock = 100.00MHz/1x10 = 1000MHz
    Initialize PASS PLL clock = 100.00MHz/2x21 = 1050.000MHz
    Initialize DDR speed = 66.67MHzx/1x20 = 1333.333MTS
    GE auto negotiation (master) two DSPs test (DSP0 -> DSP1)...

    然后就一直卡在这里一直走不下去了。请问这是怎么回事?