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am335x Ether RMII接口

weijun shao
Prodigy 80 points
Other Parts Discussed in Thread: AM3359

hi!  我的板子用了ksz8041的PHY芯片，接口部分用RMII和am3359 的MII1连接。跟beaglebone或者EVM相比，更换了PHY芯片和接口。

  我用Startware和uboot来调试网口，都发现PHY部分能正常工作，网络指示灯正常，工作模式100M duplex.

     我想请教am3359如果用rmii接口的话，除了正常的clock设置，pinmux设置外，有什么特殊的地方需要改动。

  我仔细查过clock和pinmux设置都没问题，特别对50M clk的两种方式（内部PLL和外部晶振）都试过了，包括GMII_SET模式设置都做了改动，但示波器测试，发送数据包的时候TX0,TX1都没有数据。

  能请教专家们，关于am335x RMII接口设置，还需要修改哪些地方呢？

  • 0
    TI__Mastermind 35157 points

    beaglebone上用的是RMII，你可以参考下beaglebone对应的starterware

  • 0 回复 Yaoming Qin
    Prodigy 80 points

    yaoming, beaglebone上用的也是MII不是RMII啊

  • 0 回复 weijun shao
    Prodigy 80 points

    已经找到问题，网口ok了

  • 0 回复 weijun shao
    TI__Mastermind 35157 points

    能给大家分享下是什么原因么？

  • 0 回复 Yaoming Qin
    Prodigy 80 points

    是PHY芯片的问题，am335x上只要设置对的clock和pinmux以及GMII_SEL的模式选择就可以了

  • 0 回复 weijun shao
    TI__Mastermind 35157 points

    硬件设计的问题么？ phy 一般不用怎么配置的，也可以考虑用ti的phy 看看

  • 0 回复 Yaoming Qin
    Prodigy 80 points

    PHY 是硬件设计问题，PHY基本不用配，但MDIO接口要通，需要读phyid和phyadr，以及auto negoation.

    我们不需要千兆网卡，只要10/100自适应就可以了。

    留我的邮箱地址:wjshao2009@gmail.com, 有问题还需请教TI的专家们。

  • 0 回复 weijun shao
    Intellectual 730 points

    8041我不清楚，9021的话对于phy需要修改时间延时的

  • 0 回复 Y tck
    Intellectual 616 points

    你好，我目前正在调试KSZ9021，我想让它工作在百兆模式下，我令REG 104h=0x9797，REG 105h=0x0000。但还是无法实现连接，请教一下你的时间参数是怎么配置的？谢谢

  • 0 回复 weijun shao
    Prodigy 120 points

    你好，我的是使用lan8710 RMII怎么都找不到phy

  • 0 回复 weijun shao
    Prodigy 220 points

    你好！请教个问题，我现在是可以找到phy 了，但是在DHCP分配ip地址的时候失败了，你有遇到过这种情况么？

  • 0 回复 fa linag
    TI__Mastermind 21947 points

    静态设置可以吗？你说的问题已经到了网际协议了，不属于硬件范畴

  • 0 回复 Holly Gu
    Prodigy 220 points

    starterware 用的是rgmii的接口配置，而我修改成了gmii 的配置方式，引脚这些都配置过了，还有模式也设置为了gmii的模式了，但是我觉得有可能是这个部分的原因，因为在跑原来的rgmii例程的时候是可以跑通的，修改之后就出现DHCP分配不到IP的情况。修改代码如下：

    #define CPSW_RGMII_SEL_MODE (0x02u)
    #define CPSW_MDIO_SEL_MODE (0x00u)
    #define LEN_MAC_ADDR (0x06u)
    #define OFFSET_MAC_ADDR (0x30u)
    #define I2C_SLAVE_EEPROM (0xA0u)


    #define CPSW_MII_SEL_MODE (0x00u)

    void CPSWPinMuxSetup(void)
    {
    #if 0
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(0)) =
    CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(1)) =
    CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
    | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(2)) =
    CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(3)) =
    CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(4)) =
    CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(5)) =
    CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(6)) =
    CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(7)) =
    CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
    | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(8)) =
    CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
    | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(9)) =
    CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
    | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(10)) =
    CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
    | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(11)) =
    CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
    | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_COL) =
    CONTROL_CONF_MII1_COL_CONF_MII1_COL_RXACTIVE
    | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_CRS) =
    CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_RXACTIVE
    | CPSW_RGMII_SEL_MODE;

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXERR) =
    CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE
    | CPSW_RGMII_SEL_MODE;

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXEN) =
    CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXDV) =
    CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_RXACTIVE
    | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD3) =
    CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD2) =
    CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD1) =
    CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD0) =
    CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXCLK) = 0x00000020u | 0x02u;
    //CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXCLK) =
    CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_RXACTIVE
    | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD3) =
    CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_RXACTIVE
    | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD2) =
    CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_RXACTIVE
    | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD1) =
    CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_RXACTIVE
    | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD0) =
    CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_RXACTIVE
    | CPSW_RGMII_SEL_MODE;

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_RMII1_REFCLK) =
    CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RXACTIVE;

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_DATA) =
    CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_RXACTIVE
    | CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_PUTYPESEL
    | CPSW_MDIO_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_CLK) =
    CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_PUTYPESEL
    | CPSW_MDIO_SEL_MODE;

    #endif

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_COL) =
    CONTROL_CONF_MII1_COL_CONF_MII1_COL_RXACTIVE | CPSW_MII_SEL_MODE;

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_CRS) =
    CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_RXACTIVE | CPSW_MII_SEL_MODE;

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXERR) =
    CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE | CPSW_MII_SEL_MODE;

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXEN) = CPSW_MII_SEL_MODE;

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXDV) =
    CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_RXACTIVE | CPSW_MII_SEL_MODE;

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD3) = CPSW_MII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD2) = CPSW_MII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD1) = CPSW_MII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD0) = CPSW_MII_SEL_MODE;

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXCLK) =
    CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_RXACTIVE | CPSW_MII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXCLK) =
    CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_RXACTIVE | CPSW_MII_SEL_MODE;

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD3) =
    CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_RXACTIVE | CPSW_MII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD2) =
    CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_RXACTIVE | CPSW_MII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD1) =
    CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_RXACTIVE | CPSW_MII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD0) =
    CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_RXACTIVE | CPSW_MII_SEL_MODE;

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_DATA) =
    CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_RXACTIVE
    | CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_PUTYPESEL
    | CPSW_MDIO_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_CLK) =
    CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_PUTYPESEL | CPSW_MDIO_SEL_MODE;

    }

    void EVMPortRGMIIModeSelect(void)
    {
    /* Select RGMII, Internal Delay mode */
    HWREG(SOC_CONTROL_REGS + CONTROL_GMII_SEL) = 0x00; //0x0A;
    }

  • 0 回复 Y tck
    Prodigy 80 points
    您好，请问9031需要对phy进行什么处理吗？我用的am335x和ksz9031。但是ping不通