现在我们的C6678与FPGA相连，需要调SRIO接口。看到TI的PDK中例子较复杂，请问有没有较简单的使用DirectIO 的例程？
Andy
你好，
1，此程序在我这链接不过。
2，我把需要的摘出来后新建工程通过了。
3，loopback_mode= SRIO_DIGITAL_LOOPBACK 时没有问题。
4，loopback_mode= SRIO_SERDES_LOOPBACK ;时在EVM上出错：
[C66xx_0] SRIO_SERDES_LOOPBACK test start............................................
[C66xx_0] Initialize main PLL = x10/1
[C66xx_0] Initialize DDR PLL = x20/1
[C66xx_0] configure DDR at 666 MHz
[C66xx_0] SRIO link speed is 5.000Gbps
[C66xx_0] SRIO path configuration 1xLaneA
[C66xx_0] SWRITE from 0x10802200 to 0x10806200, 8 bytes, 4086 cycles, 15 Mbps, completion code = 0
[C66xx_0] SWRITE from 0x10802200 to 0x10806200, 16 bytes, 4372 cycles, 29 Mbps, completion code = 0
[C66xx_0] data mismatch at unit 0, 0x2 (at 0x10802200) != 0xffffffff (at 0x10806200)
[C66xx_0] SWRITE from 0x10802200 to 0x10806200, 32 bytes, 4364 cycles, 58 Mbps, completion code = 0
[C66xx_0] data mismatch at unit 0, 0x3 (at 0x10802200) != 0xffffffff (at 0x10806200)
[C66xx_0] SWRITE from 0x10802200 to 0x10806200, 64 bytes, 4654 cycles, 110 Mbps, completion code = 0
[C66xx_0] data mismatch at unit 0, 0x4 (at 0x10802200) != 0xffffffff (at 0x10806200)
[C66xx_0] SWRITE from 0x10802200 to 0x10806200, 128 bytes, 5310 cycles, 192 Mbps, completion code = 0
[C66xx_0] data mismatch at unit 0, 0x5 (at 0x10802200) != 0xffffffff (at 0x10806200)
[C66xx_0] SWRITE from 0x10802200 to 0x10806200, 256 bytes, 6332 cycles, 323 Mbps, completion code = 0
[C66xx_0] data mismatch at unit 0, 0x6 (at 0x10802200) != 0xffffffff (at 0x10806200)
5，怀疑是修改程序出错，于是加载论坛中的.out，修改008254c0 loopback_mode =2（SRIO_SERDES_LOOPBACK ），运行，结果一样，如下
请问有可能是哪里设置错误了？
谢谢！
