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28377D的GPIO触发CPU2的EXINT5中断问题

配置GPIO_13为输入,并且配置为EXINT5的触发引脚,然后配置CPU2,打开EXINT5中断使能,开PIE总中断,开EXINT5中断位,CPU2中断触发不了。

然后在CPU1打开EXINT5中断使能,开PIE总中断,开EXINT5中断位,CPU1和CPU2的中断就能触发,请问是什么问题?

查看数据手册说两个CPU的PIE中断是独立的。

  • CPU1的代码如下

    void EXINT5INIT(void)
    {

    GPIO_SetupPinMux(13, GPIO_MUX_CPU2, 0);
    GPIO_SetupPinOptions(13, GPIO_INPUT, GPIO_ASYNC);
    GPIO_SetupXINT5Gpio(13);

    EALLOW;
    PieVectTable.XINT5_INT = &EXINT5INIT_isr;

    XintRegs.XINT5CR.bit.POLARITY = 0; // Falling edge interrupt
    // Enable XINT5
    XintRegs.XINT5CR.bit.ENABLE = 1; // Enable XINT5
    EDIS;
    PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
    PieCtrlRegs.PIEIER12.bit.INTx3 = 1; // Enable PIE Group 12 INT3
    IER |= M_INT12; // Enable CPU INT12

    EINT;
    }

    CPU2的代码如下

    void EXINT5INIT(void)
    {
    EALLOW;
    PieVectTable.XINT5_INT = &EXFPGAADCint_isr1;

    XintRegs.XINT5CR.bit.POLARITY = 0; // Falling edge interrupt
    // Enable XINT5
    XintRegs.XINT5CR.bit.ENABLE = 1; // Enable XINT5
    EDIS;
    PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
    PieCtrlRegs.PIEIER12.bit.INTx3 = 1; // Enable PIE Group 12 INT3
    IER |= M_INT12; // Enable CPU INT12

    EINT;
    }

    只有把CPU1的中断打开,这样CPU2才能触发中断,如果将CPU1的PieCtrlRegs.PIEIER12.bit.INTx3 = 1; // Enable PIE Group 12 INT3屏蔽掉,CPU2中断就触发不了,请大神指教。

  • 您好,

    在不开cpu1中断的时候debug,gpio13脚有信号过来时,有无查看下该管脚的状态是否发生改变。

  • 当时给的触发信号是10K的,DEBUG的时候看不出来变化。

    关中断和IO状态有关系吗?