请问一下，我编写了一个调试程序，使用PWM触发ADC工作，ADC触发CLA，在CLA中进行相关计算，但是我通过强制触发可以启动CLA计算，但是使用ADC就无法进行触发，ADC是能正常工作的，请问哪儿不正确，下面是相关程序，我使用的C编写的CLA代码。
主程序：
#include "DSP28x_Project.h" // DSP28x Headerfile
#include "F2806x_Cla_defines.h"
#include "SensorCla.h"
extern float fAngle;
extern float fResult;
float Buf;
__interrupt void adc_isr(void);
// Main Function
void main(void)
{
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2806x_SysCtrl.c file.
InitSysCtrl();
// Step 2. Initialize GPIO:
// This example function is found in the F2806x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio(); // Skipped for this example
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2806x_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in F2806x_DefaultIsr.c.
// This function is found in F2806x_PieVect.c.
InitPieVectTable();
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart,(Uint32)&RamfuncsLoadEnd);
// Call Flash Initialization to setup flash waitstates
// This function must reside in RAM
InitFlash();
EALLOW; // This is needed to write to EALLOW protected register
PieVectTable.ADCINT1 = &adc_isr;
EDIS; // This is needed to disable write to EALLOW protected registers
//Init Function
Init_Adc();
Init_Pwm();
Init_Cla();
/* Enable CLA interrupts at the group and subgroup levels */
PieCtrlRegs.PIEIER11.bit.INTx1 = 1;
PieCtrlRegs.PIEIER1.bit.INTx1 = 1;
IER |= M_INT1;
IER |= M_INT11 ;
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
for(;;){
// Cla1ForceTask1andWait();
Buf = fResult;
}
}
__interrupt void adc_isr(void)
{
AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //Clear ADCINT1 flag reinitialize for next SOC
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
return;
}
ADC初始化程序：
InitAdc();
AdcOffsetSelfCal();
EALLOW;
AdcRegs.ADCCTL2.bit.ADCNONOVERLAP = 1; // Enable non-overlap mode
AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1; // ADCINT1 trips after AdcResults latch
AdcRegs.INTSEL1N2.bit.INT1E = 1; // Enabled ADCINT1
AdcRegs.INTSEL1N2.bit.INT1CONT = 1; // Disable ADCINT1 Continuous mode
AdcRegs.INTSEL1N2.bit.INT1SEL = 1; // setup EOC1 to trigger ADCINT1 to fire
AdcRegs.ADCSOC0CTL.bit.CHSEL = 4; // set SOC0 channel select to ADCINA4
AdcRegs.ADCSOC1CTL.bit.CHSEL = 2; // set SOC1 channel select to ADCINA2
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 5; // set SOC0 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 5; // set SOC1 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC0CTL.bit.ACQPS = 6; // set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC1CTL.bit.ACQPS = 6; // set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
EDIS;
CLA初始化程序：
void Init_Cla()
{
/* Assign user defined ISR to the PIE vector table */
EALLOW;
PieVectTable.CLA1_INT1 = &cla1_task1_isr;
PieVectTable.CLA1_INT2 = &cla1_task2_isr;
PieVectTable.CLA1_INT3 = &cla1_task3_isr;
PieVectTable.CLA1_INT4 = &cla1_task4_isr;
PieVectTable.CLA1_INT5 = &cla1_task5_isr;
PieVectTable.CLA1_INT6 = &cla1_task6_isr;
PieVectTable.CLA1_INT7 = &cla1_task7_isr;
PieVectTable.CLA1_INT8 = &cla1_task8_isr;
EDIS;
//Copy over the CLA code(if running in standalone mode from FLASH)
memcpy(&Cla1funcsRunStart, &Cla1funcsLoadStart, (Uint32)&Cla1funcsLoadEnd);
//Copy over the CLA math tables(if running in standalone mode from FLASH
//and using the CLAMath Library)
memcpy(&Cla1mathTablesRunStart, &Cla1mathTablesLoadStart, (Uint32)&Cla1mathTablesLoadEnd);
/* Compute all CLA task vectors */
EALLOW;
Cla1Regs.MVECT1 = (Uint16)((Uint32)&Cla1Task1 -(Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT2 = (Uint16)((Uint32)&Cla1Task2 -(Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT3 = (Uint16)((Uint32)&Cla1Task3 -(Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT4 = (Uint16)((Uint32)&Cla1Task4 -(Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT5 = (Uint16)((Uint32)&Cla1Task5 -(Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT6 = (Uint16)((Uint32)&Cla1Task6 -(Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT7 = (Uint16)((Uint32)&Cla1Task7 -(Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT8 = (Uint16)((Uint32)&Cla1Task8 -(Uint32)&Cla1Prog_Start);
EDIS;
// Step 3 : Mapping CLA tasks
/* All tasks are enabled and will be started by an ePWM trigger
* Map CLA program memory to the CLA and enable software breakpoints
*/
EALLOW;
Cla1Regs.MPISRCSEL1.bit.PERINT1SEL = CLA_INT1_ADCINT1;
Cla1Regs.MPISRCSEL1.bit.PERINT2SEL = CLA_INT2_ADCINT2;
Cla1Regs.MPISRCSEL1.bit.PERINT3SEL = CLA_INT3_ADCINT3;
Cla1Regs.MPISRCSEL1.bit.PERINT4SEL = CLA_INT4_ADCINT4;
Cla1Regs.MPISRCSEL1.bit.PERINT5SEL = CLA_INT5_ADCINT5;
Cla1Regs.MPISRCSEL1.bit.PERINT6SEL = CLA_INT6_ADCINT6;
Cla1Regs.MPISRCSEL1.bit.PERINT7SEL = CLA_INT7_ADCINT7;
Cla1Regs.MPISRCSEL1.bit.PERINT8SEL = CLA_INT8_ADCINT8;
Cla1Regs.MIER.all = 0xff;
EDIS;
/* Switch the CLA program space to the CLA and enable software forcing
* Also switch over CLA data ram 0,1 and 2
* CAUTION: The RAMxCPUE bits can only be enabled by writing to the register
* and not the individual bit field. Furthermore, the status of these bitfields
* is not reflected in either the watch or register views - they always read as
* zeros. This is a known bug and the user is advised to test CPU accessibilty
* first before proceeding
*/
EALLOW;
Cla1Regs.MMEMCFG.all = CLA_PROG_ENABLE|CLARAM0_ENABLE|CLARAM1_ENABLE|CLARAM2_ENABLE|CLA_RAM1CPUE;
Cla1Regs.MCTL.bit.IACKE = 1;
EDIS;
Cla1ForceTask8();
}
CLA程序;
/*
* Sensor_CLA_C.cla
*
* Created on: 2017年2月14日
* Author: Administrator
*/
#include "DSP28x_Project.h" // DSP28x Headerfile
#include "SensorCla.h"
#include "F2806x_EPwm.h"
#include "F2806x_Adc.h"
//Global Data used in Motor control software
// Variables used for computation on the CLA are in CLA writable space i.e. the CLA data RAM
#pragma DATA_SECTION(rg1,"ClaDataRam0");
volatile RAMP_GEN_CLA rg1;
#pragma DATA_SECTION(rc1,"ClaDataRam0");
volatile RAMP_CNTL_CLA rc1;
#pragma DATA_SECTION(clarke1,"ClaDataRam0");
volatile CLARKE_CLA clarke1;
#pragma DATA_SECTION(park1,"ClaDataRam0");
volatile PARK_CLA park1;
#pragma DATA_SECTION(ipark1,"ClaDataRam0");
volatile iPARK_CLA ipark1;
#pragma DATA_SECTION(svgen1,"ClaDataRam0");
volatile SVGEN_CLA svgen1;
#pragma DATA_SECTION(VdTesting,"CpuToCla1MsgRAM");
volatile float VdTesting;
#pragma DATA_SECTION(pwm1,"ClaDataRam0");
volatile PWMDRV_3phInv_CLA pwm1;
#pragma DATA_SECTION(fAngle,"CpuToCla1MsgRAM")
float fAngle;
#pragma DATA_SECTION(fResult,"Cla1ToCpuMsgRAM")
float fResult;
// The C28x instructs the CLA to change the speed or close speed loop
// These variables are declared in the message RAM
#pragma DATA_SECTION(SpeedRef,"CpuToCla1MsgRAM");
volatile float SpeedRef;
#pragma DATA_SECTION(VqTesting,"CpuToCla1MsgRAM");
volatile float VqTesting;
#pragma DATA_SECTION(Test,"Cla1ToCpuMsgRAM");
volatile float Test;
#define CLA_DEBUG 0
//#define dat
interrupt void Cla1Task1 ( void )
{
#if (CLA_DEBUG==1)
__mdebugstop();
#endif
fResult = CLAasin(fAngle);
#ifdef dat
// ------------------------------------------------------------------------------
// Connect inputs of the RMP module and call the ramp control macro
// ------------------------------------------------------------------------------
rc1.TargetValue = SpeedRef;
RAMP_CNTL_CLA_MACRO(rc1)
// ------------------------------------------------------------------------------
// Connect inputs of the RAMP GEN module and call the ramp generator macro
// ------------------------------------------------------------------------------
rg1.Freq=rc1.SetpointValue;
RAMP_GEN_CLA_MACRO(rg1)
// ------------------------------------------------------------------------------
// Connect inputs of the INV_PARK module and call the inverse park trans. macro
// ------------------------------------------------------------------------------
ipark1.d=VdTesting;
ipark1.q=VqTesting;
ipark1.cos=CLAcosPU(rg1.Out);
ipark1.sine=CLAsinPU(rg1.Out);
iPARK_CLA_MACRO(ipark1)
// ------------------------------------------------------------------------------
// Connect inputs of the SVGEN module and call the space-vector gen. macro
// ------------------------------------------------------------------------------
svgen1.Ualpha=ipark1.alpha;
svgen1.Ubeta=ipark1.beta;
SVGEN_CLA_MACRO(svgen1)
// ------------------------------------------------------------------------------
// Connect inputs of the PWM_DRV module and call the PWM signal generation macro
// ------------------------------------------------------------------------------
pwm1.MfuncC1=svgen1.Ta;
pwm1.MfuncC2=svgen1.Tb;
pwm1.MfuncC3=svgen1.Tc;
Test = pwm1.MfuncC1;
PWMDRV_3phInv_CLA_MACRO(pwm1)
// ------------------------------------------------------------------------------
// Connect inputs of the PWMDAC module
// ------------------------------------------------------------------------------
PWMDRV_DAC_CLA_MACRO(park1.d,park1.q,park1.theta,clarke1.beta,500)
#endif
}
interrupt void Cla1Task2 ( void )
{
#if (CLA_DEBUG==1)
__mdebugstop();
#endif
fResult = CLAasin(fAngle);
}
interrupt void Cla1Task3 ( void )
{
#if (CLA_DEBUG==1)
__mdebugstop();
#endif
fResult = CLAasin(fAngle);
}
interrupt void Cla1Task4 ( void )
{
#if (CLA_DEBUG==1)
__mdebugstop();
#endif
fResult = CLAasin(fAngle);
}
interrupt void Cla1Task5 ( void )
{
#if (CLA_DEBUG==1)
__mdebugstop();
#endif
fResult = CLAasin(fAngle);
}
interrupt void Cla1Task6 ( void )
{
#if (CLA_DEBUG==1)
__mdebugstop();
#endif
fResult = CLAasin(fAngle);
}
interrupt void Cla1Task7 ( void )
{
#if (CLA_DEBUG==1)
__mdebugstop();
#endif
fResult = CLAasin(fAngle);
}
interrupt void Cla1Task8 ( void )
{
#if (CLA_DEBUG==1)
__mdebugstop();
#endif
// Keep your module initialization code that needs to be performed by the CLA here
RAMP_CNTL_CLA_INIT(rc1)
RAMP_GEN_CLA_INIT(rg1)
iPARK_CLA_INIT(ipark1)
SVGEN_CLA_INIT_MACRO(svgen1)
pwm1.HalfPerMax=500;
}
下面是CMD文件的配置：
CLA_SCRATCHPAD_SIZE = 0x100; // If using --define CLA_SCRATCHPAD_SIZE=0x100, remove this line
_Cla1Prog_Start = _Cla1funcsRunStart;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
MEMORY
{
PAGE 0 : /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
CLAProg : origin = 0x009000, length = 0x001000 /* on-chip RAM block L3 */
C28Prog : origin = 0x00A000, length = 0x002000 /* on-chip RAM block L4 */
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
FLASHH : origin = 0x3D8000, length = 0x004000 /* on-chip FLASH */
FLASHG : origin = 0x3DC000, length = 0x004000 /* on-chip FLASH */
FLASHF : origin = 0x3E0000, length = 0x004000 /* on-chip FLASH */
FLASHE : origin = 0x3E4000, length = 0x004000 /* on-chip FLASH */
FLASHD : origin = 0x3E8000, length = 0x004000 /* on-chip FLASH */
FLASHC : origin = 0x3EC000, length = 0x004000 /* on-chip FLASH */
FLASHA : origin = 0x3F4000, length = 0x003F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL_P0 : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
FPUTABLES : origin = 0x3FD860, length = 0x0006A0 /* FPU Tables in Boot ROM */
IQTABLES : origin = 0x3FDF00, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEA50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEADC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
ROM : origin = 0x3FF3B0, length = 0x000C10 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
CLARAM0 : origin = 0x008800, length = 0x000400 /* CLA RAM0 2K */
CLARAM1 : origin = 0x008C00, length = 0x000400 /* CLA RAM1 1K */
CLARAM2 : origin = 0x008000, length = 0x000800 /* CLA RAM2 1K */
dataRam : origin = 0x00C000, length = 0x002000 /* on-chip RAM block L5 */
RAML6 : origin = 0x00E000, length = 0x002000 /* on-chip RAM block L6 */
RAML7 : origin = 0x010000, length = 0x002000 /* on-chip RAM block L7 */
RAML8 : origin = 0x012000, length = 0x002000 /* on-chip RAM block L8 */
USB_RAM : origin = 0x040000, length = 0x000800 /* USB RAM */
FLASHB : origin = 0x3F0000, length = 0x004000 /* on-chip FLASH */
CLA_CPU_MSGRAM : origin = 0x001480, length = 0x000080 /* CLA to CPU RAM */
CPU_CLA_MSGRAM : origin = 0x001500, length = 0x000080 /* CPU to CLA RAM */
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA, PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA, PAGE = 0
codestart : > BEGIN, PAGE = 0
ramfuncs : LOAD = FLASHD,
RUN = C28Prog,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0
Cla1Prog : LOAD = FLASHC, /* Note for running from RAM the load and RUN can be the same */
RUN = CLAProg,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
RUN_START(_Cla1funcsRunStart),
PAGE = 0
csmpasswds : > CSM_PWL_P0, PAGE = 0
csm_rsvd : > CSM_RSVD, PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM0, PAGE = 1
.ebss : > dataRam, PAGE = 1
.cio : > dataRam, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
/* Initalized sections to go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA, PAGE = 0
.switch : > FLASHA, PAGE = 0
/* Allocate IQ math areas: */
Cla1mathTables : LOAD = FLASHA,
RUN = C28Prog,
LOAD_START(_Cla1mathTablesLoadStart),
LOAD_END(_Cla1mathTablesLoadEnd),
RUN_START(_Cla1mathTablesRunStart),
PAGE = 0
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Allocate FPU math areas: */
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS, PAGE = 0, TYPE = DSECT
cntl_coeff_RAM : > dataRam, PAGE=1
cntl_var_RAM : > dataRam, PAGE =1
Cla1ToCpuMsgRAM : > CLA_CPU_MSGRAM PAGE = 1
CpuToCla1MsgRAM : > CPU_CLA_MSGRAM PAGE = 1
ClaDataRam0 : > CLARAM0, PAGE = 1
ClaDataRam1 : > CLARAM1, PAGE = 1
ClaDataRam2 : > CLARAM2, PAGE = 1
CLAmathTables : > CLARAM1, PAGE = 1
CLA1mathTables : > CLARAM1, PAGE = 1
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > CLARAM1, PAGE = 1
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
/* Uncomment the section below if calling the IQNasin() or IQasin()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
}
*/
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS, PAGE = 0, TYPE = DSECT
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
望指教！！！！！！！！！！！！！！！！！
