求助:
用28335芯片的XINTF连接外扩的SRAM和FLASH,ZONE6-连接下图中的左边SRAM,ZONE7连接下图1中右边的FLASH.
当SRAM片选时(把图2中的跳线帽接上),FLASH一直可以进行擦除,
当SRAM不片选时(把图2中的跳线帽不接),FLASH擦除出现问题。
ZONE6和ZONE7的地址线和数据线是公用的。
为什么ZONE6中SRAM的片选信号会影响ZONE7的FLASH?????
代码如下:
void InitXintf16Gpio() { EALLOW; GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3; // XD15 GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3; // XD14 GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3; // XD13 GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3; // XD12 GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3; // XD11 GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3; // XD10 GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3; // XD19 GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3; // XD8 GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // XD7 GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // XD6 GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // XD5 GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // XD4 GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // XD3 GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // XD2 GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // XD1 GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // XD0 GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // XA0/XWE1n GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3; // XA1 GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; // XA2 GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; // XA3 GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3; // XA4 GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3; // XA5 GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3; // XA6 GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3; // XA7 GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3; // XA8 GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3; // XA9 GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3; // XA10 GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3; // XA11 GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; // XA12 GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; // XA13 GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; // XA14 GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; // XA15 GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // XA16 GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3; // XA17 GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3; // XA18 // GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // XA19 GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // XREADY GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // XRNW GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // XWE0 GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3; // XZCS0 GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // XZCS7 GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // XZCS6 EDIS; }
}