在调试使用dsp28035的cla过程中，发现debug情况下运行正常！！拔掉debug让芯片自动运行时，发现主cpu运行正常，ADC,CAN模块都运行正常，但是cla整个控制PWM输出完全乱了！！PWM有输出 只是她的值完全是乱的，是不是哪没有初始化？？下面是我cla 的cmd和cla初始化！！求解！！
MEMORY
{
/*Program Space*/
PAGE 0:
RAML0 : origin = 0x008000, length = 0x000800 /* on-chip RAM (L0)*/
RAML3 : origin = 0x009000, length = 0x001000 /* data RAM (L3) */
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
FLASHH : origin = 0x3E8000, length = 0x002000 /* on-chip FLASH */
FLASHG : origin = 0x3EA000, length = 0x002000 /* on-chip FLASH */
FLASHF : origin = 0x3EC000, length = 0x002000 /* on-chip FLASH */
FLASHE : origin = 0x3EE000, length = 0x002000 /* on-chip FLASH */
FLASHD : origin = 0x3F0000, length = 0x001000 /* on-chip FLASH */
FLASHC : origin = 0x3F1000, length = 0x001000 /* on-chip FLASH */
FLASHA : origin = 0x3F3000, length = 0x004F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
IQTABLES : origin = 0x3FE000, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEBDC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
BOOTROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
/*Data Space*/
PAGE 1 :
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x000300 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000350, length = 0x000500 /* on-chip RAM block M1 */
CLARAM0 : origin = 0x008850, length = 0x000350 /* on-chip RAM block L1 */
CLARAM1 : origin = 0x008C00, length = 0x000400 /* on-chip RAM block L2 */
CLA_CPU_MSGRAM : origin = 0x001480, length = 0x000080 /* CLA-R/W, CPU-R message RAM */
CPU_CLA_MSGRAM : origin = 0x001500, length = 0x000080 /* CPU-R/W, CLA-R message RAM */
FLASHB : origin = 0x3F2000, length = 0x001000 /* on-chip FLASH */
}
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA, PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA, PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = FLASHD,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0
.bss_cla : > CLARAM1, PAGE = 1
Cla1Prog : LOAD = FLASHC, /* Note for running from RAM the load and RUN can be the same */
RUN = RAML3,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
RUN_START(_Cla1funcsRunStart),
PAGE = 0
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM0, PAGE = 1
.ebss : > RAMM1, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA PAGE = 0
.switch : > FLASHA PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHD PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES PAGE = 0, TYPE = NOLOAD /* Math Tables In ROM */
Cla1ToCpuMsgRAM : > CLA_CPU_MSGRAM PAGE = 1
CpuToCla1MsgRAM : > CPU_CLA_MSGRAM PAGE = 1
ClaDataRam0 : > CLARAM0, PAGE = 1
ClaDataRam1 : > CLARAM1, PAGE = 1
CLAmathTables : > CLARAM1, PAGE = 1
CLA1mathTables : > CLARAM1, PAGE = 1
//
// Must be allocated to memory the CLA has write access to
//
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > CLARAM0, PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
/* Uncomment the section below if calling the IQNasin() or IQasin()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
}
*/
}
void CLA_C_Init()
{
// This code assumes the CLA clock is already enabled in
// the call to DevInit();
//
// EALLOW: is needed to write to EALLOW protected registers
// EDIS: is needed to disable write to EALLOW protected registers
//
// The symbols used in this calculation are defined in the CLA
// assembly code and in the CLAShared.h header file
EALLOW;
Cla1Regs.MVECT1 = ((Uint16)Cla1Task1 - (Uint16)&Cla1Prog_Start);
Cla1Regs.MVECT2 = ((Uint16)Cla1Task2 - (Uint16)&Cla1Prog_Start);
Cla1Regs.MVECT3 = ((Uint16)Cla1Task3 - (Uint16)&Cla1Prog_Start);
Cla1Regs.MVECT4 = ((Uint16)Cla1Task4 - (Uint16)&Cla1Prog_Start);
Cla1Regs.MVECT5 = ((Uint16)Cla1Task5 - (Uint16)&Cla1Prog_Start);
Cla1Regs.MVECT6 = ((Uint16)Cla1Task6 - (Uint16)&Cla1Prog_Start);
Cla1Regs.MVECT7 = ((Uint16)Cla1Task7 - (Uint16)&Cla1Prog_Start);
Cla1Regs.MVECT8 = ((Uint16)Cla1Task8 - (Uint16)&Cla1Prog_Start);
// Copy the CLA program code from its load address to the CLA program memory
// Once done, assign the program memory to the CLA
//
// Make sure there are at least two SYSCLKOUT cycles between assigning
// the memory to the CLA and when an interrupt comes in
// Call this function even if Load and Run address is the same!
MemCopy(&Cla1funcsLoadStart, &Cla1funcsLoadEnd, &Cla1funcsRunStart);
asm(" RPT #3 || NOP");
Cla1Regs.MMEMCFG.bit.PROGE = 1; // Configure the RAM as CLA program memory
Cla1Regs.MMEMCFG.bit.RAM0E = 1; // configure RAM L1, F28035 as CLA Data memory 0
Cla1Regs.MMEMCFG.bit.RAM1E = 1; // Configure RAM L2, F28035 as CLA data memory 1
// Enable the IACK instruction to start a task
// Enable the CLA interrupt 8 and interrupt 2
asm(" RPT #3 || NOP");
Cla1Regs.MCTL.bit.IACKE = 1;
Cla1Regs.MIER.all = M_INT8;
// No need to wait, the task will finish by the time
// we configure the ePWM and ADC modules
Cla1ForceTask8();
EDIS;
}