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F28M35是安全级的芯片吗?

Other Parts Discussed in Thread: CONTROLSUITE

我记得以前好像看到过官网上说F28M35通过了IEC61508,但是现在又找不到了

  • F28M35没有过这个标准的,TI的安全芯片是Hercules, 通过了61508、62262等,建议在safety网页上寻找:

    http://www.ti.com/ww/en/functional_safety/safeti/SafeTI-61508.html

     

  • 在TI的这个文档SPRT641A中,确实有讲到它是符合SafeTI-61508/ SIL-3的,曾经咨询过TI的FAE,说是在以后的RoadMap中有做认证的计划。但不知为什么,现在还没通过?不过看它里面的架构,与Safe MCU---TMS470/570/RM48X相比,通过的可能性不大?

  • 见附件!SafeTI System Design Packages for Functional Safety.pdf--------SPRT641A,以前在TI官网上下的,刚才在TI官网上搜了半天,好像没有了!什么情况!估计就不做认证了!

    SafeTI System Design Packages for Functional Safety.pdf
  • Anfu,

    目前看上去还没有,你的具体要求是什么?可以考虑TMS570等安全的芯片。

  • Hi Martin !

    能回答一下关于F28M35的ADC的中断问题的问题吗? 亟待解决!

    最近在用TIConcerto系列F28M35H52C 做一个模拟信号采集的项目。在ADC方面遇到一些问题。不知是否方便予以解答。前两天在deyisupport上发过帖子,但没人回答,故现在想你求援。

         问题描述:在我的设计中,ADC1/ADC2采用overlap、依次顺序进行转换,各SOC0--SOC15均采用定时器TINT1100us定时去触发,当SOC15转换完毕后去触发ADCINT1(ADC2SOC15触发ADCINT2)ADCINT1/ADCINT2PIE中不允许中断,通过查询中断标记位判断16SOC转换是否完成。在程序中在各步加设GIO10的方式,通过示波器观察各步的执行时间和状态,发现采用查询ADCINT1中断标记位时,从ADC启动(通过TINT1启动)到ADC1 的中断标记置位时的时间间隔只有惊人的0.8us这么短,那可是16SOC的转换啊!根据TISPRUH22FP900到的参数,应该是543ns X 16=8.5us左右,差距是10倍左右!而采用查询ADCCTL1.bit.ADCBSYADCCTL1.bit.ADCBSYCHN方式,测得到SOC15转换完毕的时间大约8us,还算靠谱! 通过设置断点,发现在中断标记为置位时,ADCBSY=1,且ADCBSYCHN=2,说明在SOC1转换完毕时,就触发了中断!但在初始化代码中,明明是设置的SOC15

    Adc1Regs.INTSEL1N2.bit.INT1SEL = 15;                         // setup ADC1 EOC15 to trigger ADCINT1

    不知是什么原因。

    我的问题就是:如何通过查询相关的ADCINT1中断标记位,判断16SOC转换是否完成?

    ADCINT1/ADCINT2TINT1均允许中断,但在PIE中却不允许中断,通过查询方式进行判断。

    以下是相关的程序代码,请帮忙看看是否有问题!谢谢! 

    由于自己设计的硬件还在打样中。所以目前硬件用的还是Concerto F28M35xx controlCARD。软件是在\ti\controlSUITE\device_support\f28m36x\v206修改的。

     EALLOW;

    Adc1Regs.ADCCTL1.bit.ADCBGPWD = 1;     // Power ADC1 BG, Bandgap circuit(带隙基准电路上电TRM P911 ADCCTL1
    Adc1Regs.ADCCTL1.bit.ADCREFPWD = 1;   // Power reference,Reference buffers circuit power down
    Adc1Regs.ADCCTL1.bit.ADCPWDN = 1;       // Power ADC1, ADC power down
    Adc1Regs.ADCCTL1.bit.ADCENABLE = 1;    // Enable ADC1
    Adc1Regs.ADCCTL1.bit.ADCREFSEL = 0;    // Select interal BG, Internal/external reference select

    Adc1Regs.ADCCTL2.bit.ADCNONOVERLAP = 0;             // 0--Enable overlap mode 
    Adc1Regs.ADCCTL1.bit.INTPULSEPOS = 1;                   // ADCINT1 trips after AdcResults latch
    Adc1Regs.INTSEL1N2.bit.INT1E = 1;                               // Enabled ADCINT1
    Adc1Regs.INTSEL1N2.bit.INT1CONT = 0;                       // Disable ADCINT1 Continuous mode
    Adc1Regs.INTSEL1N2.bit.INT1SEL = 15;                         // setup ADC1 EOC15 to trigger ADCINT1
    Adc1Regs.SOCPRICTL.bit.SOCPRIORITY = 15;             // 15: SOC0-SOC14 are high priority, SOC15 is in round robin mode.

    AnalogSysctrlRegs.TRIG1SEL.all     = 2;     // Assigning TINT1 (CPU Timer 1) to ADC TRIGGER 1 of the ADC1 and ADC2 module 

    Adc1Regs.ADCSOC0CTL.bit.CHSEL = 0; // set SOC0 channel select to ADC1A0 
    Adc1Regs.ADCSOC1CTL.bit.CHSEL = 8; // set SOC1 channel select to ADC1B0
    Adc1Regs.ADCSOC2CTL.bit.CHSEL = 4; // set SOC2 channel select to ADC1A4
    Adc1Regs.ADCSOC3CTL.bit.CHSEL = 12; // set SOC3 channel select to ADC1B4
    Adc1Regs.ADCSOC4CTL.bit.CHSEL = 0; // set SOC4 channel select to ADC1A0
    Adc1Regs.ADCSOC5CTL.bit.CHSEL = 8; // set SOC5 channel select to ADC1B0
    Adc1Regs.ADCSOC6CTL.bit.CHSEL = 4; // set SOC6 channel select to ADC1A4
    Adc1Regs.ADCSOC7CTL.bit.CHSEL = 12; // set SOC7 channel select to ADC1B4
    Adc1Regs.ADCSOC8CTL.bit.CHSEL = 0; // set SOC8 channel select to ADC1A0
    Adc1Regs.ADCSOC9CTL.bit.CHSEL = 8; // set SOC9 channel select to ADC1B0
    Adc1Regs.ADCSOC10CTL.bit.CHSEL = 4; // set SOC10 channel select to ADC1A4
    Adc1Regs.ADCSOC11CTL.bit.CHSEL = 12; // set SOC11 channel select to ADC1B4
    Adc1Regs.ADCSOC12CTL.bit.CHSEL = 0; // set SOC12 channel select to ADC1A0
    Adc1Regs.ADCSOC13CTL.bit.CHSEL = 8; // set SOC13 channel select to ADC1B0
    Adc1Regs.ADCSOC14CTL.bit.CHSEL = 4; // set SOC14 channel select to ADC1A4
    Adc1Regs.ADCSOC15CTL.bit.CHSEL = 12; // set SOC15 channel select to ADC1B4

    Adc1Regs.ADCSOC0CTL.bit.TRIGSEL = 5; // Set SOC0 start trigger to ADC Trigger 1 of the ADC 
    Adc1Regs.ADCSOC1CTL.bit.TRIGSEL = 5; // set SOC1 start trigger to ADC Trigger 1 of the ADC
    Adc1Regs.ADCSOC2CTL.bit.TRIGSEL = 5; // Set SOC2 start trigger to ADC Trigger 1 of the ADC
    Adc1Regs.ADCSOC3CTL.bit.TRIGSEL = 5; // set SOC3 start trigger to ADC Trigger 1 of the ADC
    Adc1Regs.ADCSOC4CTL.bit.TRIGSEL = 5; // Set SOC4 start trigger to ADC Trigger 1 of the ADC
    Adc1Regs.ADCSOC5CTL.bit.TRIGSEL = 5; // set SOC5 start trigger to ADC Trigger 1 of the ADC
    Adc1Regs.ADCSOC6CTL.bit.TRIGSEL = 5; // Set SOC6 start trigger to ADC Trigger 1 of the ADC
    Adc1Regs.ADCSOC7CTL.bit.TRIGSEL = 5; // set SOC7 start trigger to ADC Trigger 1 of the ADC
    Adc1Regs.ADCSOC8CTL.bit.TRIGSEL = 5; // Set SOC8 start trigger to ADC Trigger 1 of the ADC
    Adc1Regs.ADCSOC9CTL.bit.TRIGSEL = 5; // set SOC9 start trigger to ADC Trigger 1 of the ADC
    Adc1Regs.ADCSOC10CTL.bit.TRIGSEL = 5; // Set SOC10 start trigger to ADC Trigger 1 of the ADC
    Adc1Regs.ADCSOC11CTL.bit.TRIGSEL = 5; // set SOC11 start trigger to ADC Trigger 1 of the ADC
    Adc1Regs.ADCSOC12CTL.bit.TRIGSEL = 5; // Set SOC12 start trigger to ADC Trigger 1 of the ADC
    Adc1Regs.ADCSOC13CTL.bit.TRIGSEL = 5; // set SOC13 start trigger to ADC Trigger 1 of the ADC
    Adc1Regs.ADCSOC14CTL.bit.TRIGSEL = 5; // Set SOC14 start trigger to ADC Trigger 1 of the ADC
    Adc1Regs.ADCSOC15CTL.bit.TRIGSEL = 5; // set SOC15 start trigger to ADC Trigger 1 of the ADC

    Adc1Regs.ADCSOC0CTL.bit.ACQPS = 6; // set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1) 
    Adc1Regs.ADCSOC1CTL.bit.ACQPS = 6; // set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
    Adc1Regs.ADCSOC2CTL.bit.ACQPS = 6; // set SOC2 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
    Adc1Regs.ADCSOC3CTL.bit.ACQPS = 6; // set SOC3 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
    Adc1Regs.ADCSOC4CTL.bit.ACQPS = 6; // set SOC4 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
    Adc1Regs.ADCSOC5CTL.bit.ACQPS = 6; // set SOC5 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
    Adc1Regs.ADCSOC6CTL.bit.ACQPS = 6; // set SOC6 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
    Adc1Regs.ADCSOC7CTL.bit.ACQPS = 6; // set SOC7 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
    Adc1Regs.ADCSOC8CTL.bit.ACQPS = 6; // set SOC8 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
    Adc1Regs.ADCSOC9CTL.bit.ACQPS = 6; // set SOC9 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
    Adc1Regs.ADCSOC10CTL.bit.ACQPS = 6; // set SOC10 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
    Adc1Regs.ADCSOC11CTL.bit.ACQPS = 6; // set SOC11 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
    Adc1Regs.ADCSOC12CTL.bit.ACQPS = 6; // set SOC12 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
    Adc1Regs.ADCSOC13CTL.bit.ACQPS = 6; // set SOC13 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
    Adc1Regs.ADCSOC14CTL.bit.ACQPS = 6; // set SOC14 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
    Adc1Regs.ADCSOC15CTL.bit.ACQPS = 6; // set SOC15 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)

    EDIS;

    while(CpuTimer1Regs.TCR.bit.TIF==0);                   //This flag gets set when the CPU-timer decrements to zero, 100us

    CpuTimer1Regs.TCR.bit.TIF = 1;                             // Writing a 1 to this bit clears the flag

    POINTPULSE_DAT_REG = 1;                                // GPIO31-- point pulse, point sanmple strat

    //while((Adc1Regs.ADCCTL1.bit.ADCBSY !=0) ||(Adc1Regs.ADCCTL1.bit.ADCBSYCHN != 0x0f));

                                                               // 判断BUSY是否空闲,且最后一个通道是否是SOC15

    while(Adc1Regs.ADCINTFLG.bit.ADCINT1==0);                     // 等待ADCINT1信号产生(SOC15转换完毕产生)
    Adc1Regs.ADCINTFLGCLR.bit.ADCINT1 = 1;                        // 
    清除ADCINT1中断信号

    POINTPULSE_DAT_REG = 0;                                                // high level width: 16 socs total time(include: Sample time + Conversion Time)

    以上问题,希望解答!谢谢!


  • 目前在做一个项目,UPS的开发需要软件认证,去年选择这个芯片的时候就是因为看到官网上有说这个芯片过IEC61508,现在项目开发一大半突然找不到这个消息了,这就惨了。

  • 谢谢你得文档!
    如果是这样的话,TI这玩笑就开大了,当时推广的时候是重点介绍了这方面的。
    不过安全级芯片的介绍网页http://www.ti.com/ww/en/functional_safety/safeti/SafeTI-26262.html
    里面2000系列的都在,只是过的认证都是60730这个家电标准。唯独不见28M35,估计是还在弄呢。

  •    按我的理解,F28M35x做IEC61508或SIL3认证的可能性不大!像Safe MCU---TMS570/RM48X系列,内部都是Dual CPUs的1OO1架构,而F28M35x虽然也是双CPU架构,一个DSP核,一个M3核,它们只是协同工作,不具备1OO1架构,所以不满足 最基本的安全架构。如果有安全级别的需求,还是要选TMS570/RM48X系列,它们是通过认证的,在芯片的Datasheet上明确有讲到它是通过SIL3认证的。如果没有提到,那肯定就没有通过认证。

      两年前,我们在做一个门控项目时,是选C2000系列,还是选570系列,当时也比较纠结。后来选了570,现在看来,选择是正确的。还是看看TMS570/RM48X系列吧,最近新推了许多芯片,选择多。

       FYI !

  • @     您好!

       看帖子知道你在用F28M35做研发,应该是大牛了!我最近也正在用F28M35设计产品,由于没有经验,遇到点问题,进展不顺!不知是否方便给予解答?谢谢!

       问题就是:当VREG12EN接GND,即采用内部电压调整器时,在Layout时,F28M35的VDD12电源引脚:Pin11,24,55,58,66,75,90,99之间是否要在芯片外部彼此连在一起?还是各引脚只需各自接去耦电容就可以了?同理当VREG18EN接GND,VDD18的Pin1,108之间呢?

       按照以前TI的FAE的说法,这些引脚在芯片外部是可以不接在一起,因为在芯片内部已经接在一起了,只需各自接去耦电容就可以了!是这样吗?您是怎样做得呢?麻烦解答,不甚感谢!

       回答也可以发至:leeanfux@sina.com。

  • Anfu,

    建议尝试下更改下优先级:

    Adc1Regs.SOCPRICTL.bit.SOCPRIORITY = 16;  

  • Hi Martin !您好!

       Adc1Regs.SOCPRICTL.bit.SOCPRIORITY = 16也试过了,也不行!连运行状态都不对了! Adc1Regs.SOCPRICTL.bit.SOCPRIORITY = 16的意思是:All SOCs are in high priority mode, arbitrated by SOC number!而Adc1Regs.SOCPRICTL.bit.SOCPRIORITY = 0的意思是:SOC priority is handled in round robin mode for all channels。按我的理解:=16 和 =0的意义是一样的,是不是!但运行情况不同!

  • TI提供的有硬件参考电路,在controlsuite的太阳能开发套件里。控制板的电路我是完全照抄的,调试时没遇到太大问题。

  • 不是太阳能库,是controlCARDs下面的DIM100硬件啊入门模块,ORCAD打开。另外提供一份开发板的原理图供参考。

    SSD-F28M35-I原理图.pdf
  • @一方☆通行,您好!

        谢谢您的解答及原理图!从原理图来看,您用的资源较多,较高端!看来您钻研的深,向您学习!

        我的打样的硬件基本能跑了。关于当VREG12EN接GND时,F28M35的VDD12电源引脚:Pin11,24,55,58,66,75,90,99之间在芯片外部不用彼此连在一起!各引脚只需各自接去耦电容就可以了?同理当VREG18EN接GND,VDD18的Pin1,108之间也是一样!这样便于PCB的Layout时。

       我看你ADC用的较充分,那关于ADC的SOC转换序列的最后一个SOC15转换完成,您是如何查询的呢?是中断?还是查询?在调试中,通过设置断点,发现在中断标记为置位时,ADCBSY=1,且ADCBSYCHN=2,说明在SOC1转换完毕时,就触发了中断!但在初始化代码中,明明是设置的SOC15

       回答也可以发至:leeanfux@sina.com。不甚感谢!

       我曾用570的20216设计过产品,如有需求,可尽力而为!