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MSP430G2553 SPI SLAVE模式发送时没个数据发了两次?

参考倒程"msp430g2xx3_uscia0_spi_10.c"写了以下SPI通信程序,单片机作为从设备,主设备是以“字”的形式来读取信息。

设计应该是04 06 08 依次发出,但实际观察到单片机发送的是两个相同的字节。如:04 04 06 06或06 06 08 08。这是什么原因呢?

 

#include <msp430.h> 

 

 

/**

 * main.c

 */

 

int main(void)

{

  WDTCTL = WDTPW + WDTHOLD;                 // Stop watchdog timer

 // while (!(P1IN & BIT4));                   // If clock sig from mstr stays low,

                                            // it is not yet in SPI mode

 

  P1SEL = BIT1 + BIT2 + BIT4;

  P1SEL2 = BIT1 + BIT2 + BIT4;

  UCA0CTL1 = UCSWRST;                       // **Put state machine in reset**

  UCA0CTL0 |= UCCKPL + UCMSB + UCSYNC;      // 3-pin, 8-bit SPI master

  UCA0CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**

  IE2 |= UCA0RXIE;                          // Enable USCI0 RX interrupt

 

  __bis_SR_register(LPM4_bits + GIE);       // Enter LPM4, enable interrupts

}

 

// Echo character

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)

#pragma vector=USCIAB0RX_VECTOR

__interrupt void USCI0RX_ISR (void)

#elif defined(__GNUC__)

void __attribute__ ((interrupt(USCIAB0RX_VECTOR))) USCI0RX_ISR (void)

#else

#error Compiler not supported!

#endif

{

    while (!(IFG2 & UCA0TXIFG));              // USCI_A0 TX buffer ready?

    UCA0TXBUF = 0x04;

    while (!(IFG2 & UCA0TXIFG));              // USCI_A0 TX buffer ready?

    UCA0TXBUF = 0x06;

    while (!(IFG2 & UCA0TXIFG));              // USCI_A0 TX buffer ready?

    UCA0TXBUF = 0x08;

}

 

  • 我用2553测试了这个代码,没有遇到问题,我也用逻辑分析仪抓过波形了。请你检查下你的主机程序。

  • 我这里测试这个例程也没问题

  • 那就是也要观察主机的输出波形,可能是地址段数据格式不同.

    下面是波形图,

    通道1:从机发送数据;

    通道2:主机发送数据;

    通道3:主机CS

    通道4:主机时钟

    第一第二的图就是上述程序的结果,也就是可能两个运行结果:

    下面第三图是程序改成延时做间隔做对比,现在主机收到的数据是0B0B6204.

    int main(void)

    {

      WDTCTL = WDTPW + WDTHOLD;                 // Stop watchdog timer

     

     

      P1DIR &= 0xC3;

      P1REN |= 0x20;                            // P1.5 pullup

      P1IE |= 0x20;                             // P1.5 interrupt enabled

      P1IES |= 0x20;                            // P1.5 Hi/lo edge

      P1IFG &= ~0x20;                           // P1.5 IFG cleared

     // while (!(P1IN & BIT4));                   // If clock sig from mstr stays low,

                                                // it is not yet in SPI mode

     

      P1SEL = BIT1 + BIT2 + BIT4;

      P1SEL2 = BIT1 + BIT2 + BIT4;

      UCA0CTL1 = UCSWRST;                       // **Put state machine in reset**

      UCA0CTL0 |= UCCKPL + UCMSB + UCSYNC;      // 3-pin, 8-bit SPI master

      UCA0CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**

      //IE2 |= UCA0RXIE;                          // Enable USCI0 RX interrupt

       __bis_SR_register(LPM3_bits + GIE);       // Enter LPM4, enable interrupts

    }

     #pragma vector=PORT1_VECTOR

    __interrupt void Port_1(void)

     

    {

        UCA0TXBUF = 0x62;

        __delay_cycles(10);

        UCA0TXBUF = 0x04;

        __delay_cycles(10);

        UCA0TXBUF = 0x0B;

        __bis_SR_register(LPM3_bits + GIE);       // Enter LPM4, enable interrupts

     }