有大侠没？请教个问题 6972跑了二天，发现adc死了。一直只进ADC12IV_ADC12TOVIFG中断，其它中断不进了。我用串口通信执行WDTCTL = 0x00使CPU复位后，adc还是只进ADC12IV_ADC12TOVIFG中断。只有把板子重位上电，才能使ADC能正常工作。
代码如下，正常执行g_adcOVErrCnt 一直为0。以前调试时，进lpm3有时会有过采现象。但现在我没用省电，执行二天后就出现上面的现象。
请教，出现ADC12IV_ADC12TOVIFG中断后要咋控制CPU，不要出现用看门狗复位后，还一直ADC死机。
#define ADC_INNER_REF2_5 0
#if STATISTICS_SUPPORT == 1
u32 g_adcOVErrCnt = 0;
u32 g_adcOkCnt = 0;
#endif
void adcInit (void)
{
u8 i;
for(i = 0;i < ADC_NUM;i++)
{
ADC_SampleResult[i] = 0;
}
#if ADC_INNER_REF2_5 == 0
GPIO_setAsPeripheralModuleFunctionInputPin (GPIO_PORT_P1,
GPIO_PIN0 | GPIO_PIN1, GPIO_TERNARY_MODULE_FUNCTION);
#endif
ctlRotateSetMultiplexer();
P9SEL0 |= BIT4 | BIT5 | BIT6 | BIT7;
P9SEL1 |= BIT4 | BIT5 | BIT6 | BIT7;
//周期是250us
ADC12CTL0 = ADC12SHT0_4 | ADC12ON | ADC12MSC; // Sampling time(64 ADC12CLK), ADC12 on
/*用了ADC12OSC（ADC12内部时钟源）分频为1*/
ADC12CTL1 = ADC12SHP | ADC12SHS_1 | ADC12CONSEQ_1; // Use sampling timer 序列通道单次转换
ADC12CTL2 |= ADC12RES_2; // 12-bit conversion results
#if ADC_INNER_REF2_5 == 1
/*内部参考*/
// Channel2 ADC input select; Vref=VREF buffered
ADC12MCTL0 = ADC12VRSEL_1 | ADC12INCH_12;
ADC12MCTL1 = ADC12VRSEL_1 | ADC12INCH_13;
ADC12MCTL2 = ADC12VRSEL_1 | ADC12INCH_14;
ADC12MCTL3 = ADC12VRSEL_1 | ADC12INCH_15 | ADC12EOS;
#else
/*外部参考*/
// Channel2 ADC input select; Vref=VREF buffered
ADC12MCTL0 = ADC12VRSEL_14 | ADC12INCH_12;
ADC12MCTL1 = ADC12VRSEL_14 | ADC12INCH_13;
ADC12MCTL2 = ADC12VRSEL_14 | ADC12INCH_14;
ADC12MCTL3 = ADC12VRSEL_14 | ADC12INCH_15 | ADC12EOS;
#endif
ADC12IER0 = ADC12IE3;
ADC12IER2 = ADC12TOVIE | ADC12OVIE;
#if ADC_INNER_REF2_5 == 1
REFCTL0 |= REFVSEL_2 | REFON;
#else
#endif
TA0CCR0 = 7; // TA0 4K 采样频率
TA0CCR1 = 1;
TA0CCTL1 |= OUTMOD_2; // TBCCR0 toggle (ON period = ~230us)
ADC12CTL0 |= ADC12ENC; //开始转
TA0CTL = TASSEL__ACLK | MC__UP | TACLR; // ACLK, up mode
#if 0
// 输出 TA0.1
P1SEL0 |= BIT6;
P1SEL1 |= BIT6;
P1DIR |= BIT6;
#endif
}
#pragma vector = ADC12_VECTOR
__interrupt void ADC_IsrCallback (void)
{
switch (__even_in_range (ADC12IV, ADC12IV_ADC12RDYIFG))
{
case ADC12IV_NONE:
break; // Vector 0: No interrupt
case ADC12IV_ADC12OVIFG:
break; // Vector 2: ADC12MEMx Overflow
case ADC12IV_ADC12TOVIFG:
//TP1
/*
#if TP_SUPPORT == 1
P3OUT |= BIT3;
__delay_cycles (1);
P3OUT &= ~BIT3;
#endif
*/
#if STATISTICS_SUPPORT == 1
g_adcOVErrCnt ++;
#endif
break; // Vector 4: Conversion time overflow
case ADC12IV_ADC12HIIFG:
break; // Vector 6: ADC12BHI
case ADC12IV_ADC12LOIFG:
break; // Vector 8: ADC12BLO
case ADC12IV_ADC12INIFG:
break; // Vector 10: ADC12BIN
case ADC12IV_ADC12IFG0:
break; // Vector 12: ADC12MEM0 Interrupt
case ADC12IV_ADC12IFG1:
break; // Vector 14: ADC12MEM1
case ADC12IV_ADC12IFG2:
break; // Vector 16: ADC12MEM2
case ADC12IV_ADC12IFG3:
// MCP430_ENTER_FULL_SPEED()
ADC12CTL0 &= ~ADC12ENC;
ADC12CTL0 |= ADC12ENC;
#if TP_SUPPORT == 1
//TP2
PJOUT |= BIT3;
#endif
ADC_SampleResult[0] = ADC12MEM0;//这个是复用的
ADC_SampleResult[1] = ADC12MEM1;
ADC_SampleResult[2] = ADC12MEM2;
ADC_SampleResult[3] = ADC12MEM3;
PJOUT &= ~BIT3;
#if STATISTICS_SUPPORT == 1
g_adcOkCnt++;
#endif
//ctlRotateSetMultiplexer();
break; // Vector 18: ADC12MEM3
case ADC12IV_ADC12IFG4: // Vector 20: ADC12MEM4
break;
case ADC12IV_ADC12IFG5:
break; // Vector 22: ADC12MEM5
case ADC12IV_ADC12IFG6:
break; // Vector 24: ADC12MEM6
case ADC12IV_ADC12IFG7:
break; // Vector 26: ADC12MEM7
case ADC12IV_ADC12IFG8:
break; // Vector 28: ADC12MEM8
case ADC12IV_ADC12IFG9:
break; // Vector 30: ADC12MEM9
case ADC12IV_ADC12IFG10:
break; // Vector 32: ADC12MEM10
case ADC12IV_ADC12IFG11:
break; // Vector 34: ADC12MEM11
case ADC12IV_ADC12IFG12:
break; // Vector 36: ADC12MEM12
case ADC12IV_ADC12IFG13:
break; // Vector 38: ADC12MEM13
case ADC12IV_ADC12IFG14:
break; // Vector 40: ADC12MEM14
case ADC12IV_ADC12IFG15:
break; // Vector 42: ADC12MEM15
case ADC12IV_ADC12IFG16:
break; // Vector 44: ADC12MEM16
case ADC12IV_ADC12IFG17:
break; // Vector 46: ADC12MEM17
case ADC12IV_ADC12IFG18:
break; // Vector 48: ADC12MEM18
case ADC12IV_ADC12IFG19:
break; // Vector 50: ADC12MEM19
case ADC12IV_ADC12IFG20:
break; // Vector 52: ADC12MEM20
case ADC12IV_ADC12IFG21:
break; // Vector 54: ADC12MEM21
case ADC12IV_ADC12IFG22:
break; // Vector 56: ADC12MEM22
case ADC12IV_ADC12IFG23:
break; // Vector 58: ADC12MEM23
case ADC12IV_ADC12IFG24:
break; // Vector 60: ADC12MEM24
case ADC12IV_ADC12IFG25:
break; // Vector 62: ADC12MEM25
case ADC12IV_ADC12IFG26:
break; // Vector 64: ADC12MEM26
case ADC12IV_ADC12IFG27:
break; // Vector 66: ADC12MEM27
case ADC12IV_ADC12IFG28:
break; // Vector 68: ADC12MEM28
case ADC12IV_ADC12IFG29:
break; // Vector 70: ADC12MEM29
case ADC12IV_ADC12IFG30:
break; // Vector 72: ADC12MEM30
case ADC12IV_ADC12IFG31:
break; // Vector 74: ADC12MEM31
case ADC12IV_ADC12RDYIFG:
break; // Vector 76: ADC12RDY
default:
break;
}
}
