有关MSP430F5529ADC12多通道序列采样时出现的问题

Lei Shan

Other Parts Discussed in Thread: MSP430F5529

本人最近在学习MSP430F5529这块单片机，因为手头有个题目关于均流和稳压控制的，做采样环节时使用了430的ADC12多通道序列采样，有关ADC12的初始化如下：void InitADC(void)
{
    P6SEL |= BIT6+BIT7;
    P7SEL |= BIT0;
    ADC12CTL0 = ADC12ON+ADC12SHT0_8+ADC12REFON+ADC12MSC;//采样转换时间, 打开ADC12内核
    ADC12CTL1 = ADC12SHP+ADC12CONSEQ_3+ADC12SSEL_2;//多通道序列采样，时钟为MCLK（这里是4M）
    ADC12CTL1 |= ADC12CSTARTADD2+ADC12CSTARTADD1;//开始位确定
    ADC12MCTL0 = ADC12SREF_1+ADC12INCH_6;//选择MCTL0作为采样结果寄存器,A6作为输入端口，参考电压选择模式一
    ADC12MCTL1 = ADC12SREF_1+ADC12INCH_7;//选择MCTL1作为采样结果寄存器,A7作为输入端口，参考电压选择模式一
    ADC12MCTL2 = ADC12SREF_1+ADC12INCH_12+ADC12EOS;//选择MCTL2作为采样结果寄存器,A12作为输入端口，参考电压选择模式一
    ADC12IE = BIT2;
    ADC12CTL0 |= ADC12ENC;
}

ADC的中断如下

#pragma vector=ADC12_VECTOR
__interrupt void ADC12ISR (void)
{
static unsigned int m,count = 0;
float factor=0.036630;
switch(__even_in_range(ADC12IV,34))
   {
      case 0: break;                           // Vector 0: No interrupt
      case 2: break;                           // Vector 2: ADC overflow
      case 4: break;                           // Vector 4: ADC timing overflow
      case 6: break;                           // Vector 6: ADC12IFG0
      case 8: break;                           // Vector 8: ADC12IFG1
      case 10:
       CAresult[count] = ADC12MEM0;
       CBresult[count] = ADC12MEM1;
       OUresult[count] = ADC12MEM2;
       count++;
       if (count == 10)
             {
           for(m=0;m<10;m++)
           {
            current_a_ = CAresult[m]+current_a_;
            current_b_ = CBresult[m]+current_b_;
            out_u_ = OUresult[m]+out_u_;
           }
           current_a_=current_a_*factor;
           current_b_=current_b_*factor;
           out_u_ =out_u_ *factor;
               count = 0;
           flag=1;
               ADC12IE = 0x00;
             }
       break;
      case 12: break;                           // Vector 12: ADC12IFG3
      case 14: break;                           // Vector 14: ADC12IFG4
      case 16: break;                           // Vector 16: ADC12IFG5
      case 18: break;                           // Vector 18: ADC12IFG6
      case 20: break;                           // Vector 20: ADC12IFG7
      case 22: break;                           // Vector 22: ADC12IFG8
      case 24: break;                           // Vector 24: ADC12IFG9
      case 26: break;                           // Vector 26: ADC12IFG10
      case 28: break;                           // Vector 28: ADC12IFG11
      case 30: break;                           // Vector 30: ADC12IFG12
      case 32: break;                           // Vector 32: ADC12IFG13
      case 34: break;                           // Vector 34: ADC12IFG14
      default: break;
   }
}