想用DMA把内存中数据通过串口发送出去,一直不成功
void uDMAInit()
{
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);//ʹÄÜʱÖÓ
ROM_uDMAEnable();//ʹÄÜÍâÉè
ROM_uDMAControlBaseSet(pui8ControlTable);
ROM_IntEnable(INT_UDMA);
ROM_UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
//
// Put the attributes in a known state for the uDMA UART1TX channel. These
// should already be disabled by default.
//
ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_UART0TX,
UDMA_ATTR_ALTSELECT |
UDMA_ATTR_HIGH_PRIORITY |
UDMA_ATTR_REQMASK);
//
// Set the USEBURST attribute for the uDMA UART TX channel. This will
// force the controller to always use a burst when transferring data from
// the TX buffer to the UART. This is somewhat more effecient bus usage
// than the default which allows single or burst transfers.
//
ROM_uDMAChannelAttributeEnable(UDMA_CHANNEL_UART0TX, UDMA_ATTR_USEBURST);
//
// Configure the control parameters for the UART TX. The uDMA UART TX
// channel is used to transfer a block of data from a buffer to the UART.
// The data size is 8 bits. The source address increment is 8-bit bytes
// since the data is coming from a buffer. The destination increment is
// none since the data is to be written to the UART data register. The
// arbitration size is set to 4, which matches the UART TX FIFO trigger
// threshold.
//
ROM_uDMAChannelControlSet(UDMA_CHANNEL_UART0TX | UDMA_PRI_SELECT,
UDMA_SIZE_8 | UDMA_SRC_INC_8 |
UDMA_DST_INC_NONE |
UDMA_ARB_4);
//
// Set up the transfer parameters for the uDMA UART TX channel. This will
// configure the transfer source and destination and the transfer size.
// Basic mode is used because the peripheral is making the uDMA transfer
// request. The source is the TX buffer and the destination is the UART
// data register.
//
ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0TX | UDMA_PRI_SELECT,
UDMA_MODE_BASIC, g_ui8TxBuf,
(void *)(UART0_BASE + UART_O_DR),
sizeof(g_ui8TxBuf));
//
// Now both the uDMA UART TX and RX channels are primed to start a
// transfer. As soon as the channels are enabled, the peripheral will
// issue a transfer request and the data transfers will begin.
//
ROM_uDMAChannelEnable(UDMA_CHANNEL_UART0TX);
//
// Enable the UART DMA TX/RX interrupts.
//
ROM_UARTIntEnable(UART0_BASE, UART_INT_DMATX );
ROM_IntEnable(INT_UART0);
}
void usart_init_all(void)
{
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);//+
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);//??UART0
GPIOPinConfigure(GPIO_PA0_U0RX);
GPIOPinConfigure(GPIO_PA1_U0TX);
GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);//??UART????PA0 PA1
UARTConfigSetExpClk(UART0_BASE, SysClock, 115200,(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));
UARTFIFOEnable(UART0_BASE);//»¹²»È·¶¨FIFOÓëDMAÊÇ·ñÓгåÍ»
UARTDMAEnable(UART0_BASE,UART_DMA_TX);//ÊÇÄÚ´æµ½´®¿Ú£¬´®¿ÚÔÙ·¢³öÈ¥£¬DMA´«Êäµ½RX»¹ÊÇTX
ROM_UARTIntEnable(UART0_BASE,UART_INT_DMATX);
IntEnable(INT_UART0); //enable the UART interrupt
//UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_RT); //only enable RX and TX interrupts
}
void UART0IntHandler()
{
uint32_t ui32Status,ui32Mode;
ui32Status = UARTIntStatus(UART0_BASE,true);
UARTIntClear(UART0_BASE,ui32Status);
if(!ROM_uDMAChannelIsEnabled(UDMA_CHANNEL_UART0TX))
{
//
// Start another DMA transfer to UART1 TX.
//
ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0TX | UDMA_PRI_SELECT,
UDMA_MODE_BASIC, g_ui8TxBuf,
(void *)(UART0_BASE + UART_O_DR),
sizeof(g_ui8TxBuf));
//
// The uDMA TX channel must be re-enabled.
//
ROM_uDMAChannelEnable(UDMA_CHANNEL_UART0TX);
}
}