我之前一直使用的是cc2640 7*7封装的芯片，现在想换成5*5或4*4的，我用TI官方的基础例程：SimpleBLEPeripheral，修改了Board.c文件里面的宏定义：
下载运行程序，广播都不能收到。
是我修改的地方不完全么？求指教。
我之前一直使用的是cc2640 7*7封装的芯片，现在想换成5*5或4*4的，我用TI官方的基础例程：SimpleBLEPeripheral，修改了Board.c文件里面的宏定义：
下载运行程序，广播都不能收到。
是我修改的地方不完全么？求指教。
你好，
需要修改的地方是在IAR里面的OPTION里面需要设置一下：
另外，你在bleuserconfig.c文件需要更改参数：
#if defined( CC2650EM_7ID )
改为 CC2650EM_5ID
0x013800C3, // Use enhanced BLE shape
0x02010403, // Synth: Use 24 MHz XOSC as synth clock, enable phase error discard feature
0x00008463, // Synth: modify phase error discard threshold factor
0x00388473, // Synth: modify phase error discard threshold Offset
0x40014035, // Set phase error error discard count to 1 (default2) to get faster settling in TX (address)
0x177F0408, // Set phase error error discard count to 1 (default2) to get faster settling in TX (value)
0x036052AC, // Add 6 us extra to tone in front of packet
0x01AD02A3, // Compensate for 6 us added to tone in front of packet
0x01680263, // Compensate for 6 us added to tone in front of packet
0xFFFFFFFF };
#elif defined( CC13XX )
//#if defined( CC1350EM_7XD )
#if defined( CC2650EM_7ID )
regOverride_t rfRegTbl[] =
{ 0x003A4038, // Synth: Set RTRIM (POTAILRESTRIM) to 10
0x7F004020, // Synth: Set bottom fine code to 0 due to modified fine bank (fine top code unchanged at 127)
0x00404064, // Synth: Set fine start code to 0x40 due to modified fine bank
0xC0040141, // Synth: Set K1 to compensate for modified fine bank
0x0533B107, // Synth: New K1 value
0x000784A3, // Synth: Set FREF = 3.43 MHz (24 MHz / 7)
0xA47E0583, // Synth: Set loop bandwidth after lock to 80 kHz (K2)
0xEAE00603, // Synth: Set loop bandwidth after lock to 80 kHz (K3, LSB)
0x00010623, // Synth: Set loop bandwidth after lock to 80 kHz (K3, MSB)
0x841F0002, // Synth: No COMP_CAP
0x00456088, // Adjust AGC reference level
0x013800C3, // Use enhanced BLE shape
0xFFFFFFFF };
#endif // package type
#else // unknown device
#error "ERROR: Unknown device!"
