TI工程师，你好！
2.16和2.21的TI-RTOS里关于CC1310 RF example，如下实例中，这个pOverrides数组是必须要更新么。更新后，使用2.16的数组的CC1310的产品和使用2.21的数组的CC1310产品，两者是可以正常通信的吧？不管是在CC1310 revA和revB上，用这两个数组任意一个，都是可以相互正好通信的吧？数组更新后，会改善哪些东西？谢谢！
tirtos_cc13xx_cc26xx_2_21_00_06\examples\IAR\CC1310DK_7XD\rfWsnConcentrator\smartrf_settings\smartrf_settings.c
uint32_t pOverrides[] =
{
// override_use_patch_prop_genfsk.xml
// PHY: Use MCE ROM bank 4, RFE RAM patch
MCE_RFE_OVERRIDE(0,4,0,1,0,0),
// override_synth_prop_863_930_div5.xml
// Synth: Set recommended RTRIM to 7
HW_REG_OVERRIDE(0x4038,0x0037),
// Synth: Set Fref to 4 MHz
(uint32_t)0x000684A3,
// Synth: Configure fine calibration setting
HW_REG_OVERRIDE(0x4020,0x7F00),
// Synth: Configure fine calibration setting
HW_REG_OVERRIDE(0x4064,0x0040),
// Synth: Configure fine calibration setting
(uint32_t)0xB1070503,
// Synth: Configure fine calibration setting
(uint32_t)0x05330523,
// Synth: Set loop bandwidth after lock to 20 kHz
(uint32_t)0x0A480583,
// Synth: Set loop bandwidth after lock to 20 kHz
(uint32_t)0x7AB80603,
// Synth: Configure VCO LDO (in ADI1, set VCOLDOCFG=0x9F to use voltage input reference)
ADI_REG_OVERRIDE(1,4,0x9F),
// Synth: Configure synth LDO (in ADI1, set SLDOCTL0.COMP_CAP=1)
ADI_HALFREG_OVERRIDE(1,7,0x4,0x4),
// Synth: Use 24 MHz XOSC as synth clock, enable extra PLL filtering
(uint32_t)0x02010403,
// Synth: Configure extra PLL filtering
(uint32_t)0x00108463,
// Synth: Increase synth programming timeout (0x04B0 RAT ticks = 300 us)
(uint32_t)0x04B00243,
// override_phy_rx_aaf_bw_0xd.xml
// Rx: Set anti-aliasing filter bandwidth to 0xD (in ADI0, set IFAMPCTL3[7:4]=0xD)
ADI_HALFREG_OVERRIDE(0,61,0xF,0xD),
// override_phy_gfsk_rx.xml
// Rx: Set LNA bias current trim offset to 3
(uint32_t)0x00038883,
// Rx: Freeze RSSI on sync found event
HW_REG_OVERRIDE(0x6084,0x35F1),
// override_phy_gfsk_pa_ramp_agc_reflevel_0x1a.xml
// Tx: Enable PA ramping (0x41). Rx: Set AGC reference level to 0x1A.
HW_REG_OVERRIDE(0x6088,0x411A),
// Tx: Configure PA ramping setting
HW_REG_OVERRIDE(0x608C,0x8213),
// override_phy_rx_rssi_offset_5db.xml
// Rx: Set RSSI offset to adjust reported RSSI by +5 dB
(uint32_t)0x00FB88A3,
// TX power override
// Tx: Set PA trim to max (in ADI0, set PACTL0=0xF8)
ADI_REG_OVERRIDE(0,12,0xF8),
(uint32_t)0xFFFFFFFF,
};
tirtos_cc13xx_cc26xx_2_16_00_08\tirtos_cc13xx_cc26xx_2_16_00_08_examples\IAR\CC1310DK_7XD\rfWsnConcentrator\smartrf_settings\smartrf_settings.c
uint32_t pOverrides[] =
{
// override_synth_prop_863_970_div5.xml
ADI_HALFREG_OVERRIDE(0,61,0xF,0xD),
HW_REG_OVERRIDE(0x4038,0x003A),
HW_REG_OVERRIDE(0x4020,0x7F00),
HW_REG_OVERRIDE(0x4064,0x0040),
(uint32_t)0x000684A3,
(uint32_t)0xC0040141,
(uint32_t)0x0533B107,
(uint32_t)0x0A480583,
(uint32_t)0x7AB80603,
ADI_REG_OVERRIDE(1,4,0x9F),
ADI_HALFREG_OVERRIDE(1,7,0x4,0x4),
(uint32_t)0x02010403,
(uint32_t)0x00108463,
(uint32_t)0x04B00243,
// override_phy_gfsk_rx_rssi.xml
HW_REG_OVERRIDE(0x6084,0x35F1),
(uint32_t)0x00038883,
(uint32_t)0x00FB88A3,
// override_phy_agc_reflevel_0x1a.xml
HW_REG_OVERRIDE(0x6088,0x001A),
// override_phy_rx_aaf_bw_0xd.xml
ADI_HALFREG_OVERRIDE(0,61,0xF,0xD),
// override_phy_agc_reflevel_0x1a.xml
HW_REG_OVERRIDE(0x6088,0x001A),
// TX power override
ADI_REG_OVERRIDE(0,12,0xF8),
(uint32_t)0xFFFFFFFF,
};
