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6678中,EDMA从L2搬移到DDR,在EDMA前,是否需要对L2进行 cache一致性操作?

1.cache设置如下:

CACHE_setL1PSize(CACHE_L1_32KCACHE);
CACHE_setL1DSize(CACHE_L1_32KCACHE);
CACHE_setL2Size(CACHE_0KCACHE);

2.v_fft_out变量放在L2中,需要将v_fft_out开始的一段数据搬移到DDR。

是否需要对v_fft_out进行cache一致性操作?

3.

static inline void WritebackCache(void * blockPtr, Uint32 byteCnt)
{
if(byteCnt>0xFFFF*4)
byteCnt= 0xFFFF*4;
if((Uint32)blockPtr>=0x0C000000&&(Uint32)blockPtr<0x0D000000) //SL2
{
CACHE_wbL1d((void *)blockPtr, byteCnt, CACHE_WAIT);
}
else if((Uint32)blockPtr>=0x10000000) //DDR or other cores
{
CACHE_wbL2((void *)blockPtr, byteCnt, CACHE_WAIT);
}
_mfence();
_mfence();
}

代码中的最大长度为0xFFFF*4,而L1D为32k=0x8000B,上面的代码中超过了L1D的长度?