ADC3663的LVDS差分输出与xilinx的ZYNQ-7000的LVDS输入的电平匹配问题
ADC3663的供电是1.8V,ADC3663的LVDS输出给到ZYNQ-7000的BANK12,BANK12的供电是2.5V的
下图是ZYNQ-7000的LVDS接口电平要求
下图是ADC3663的LVDS接口电平要求
目前的设计是串联电阻,串联电阻对Layout有些不友好
所以想请教一下当ADC3663的LVDS输出给到ZYNQ-7000的LVDS接收这两者之间可以直连吗?
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ADC3663的LVDS差分输出与xilinx的ZYNQ-7000的LVDS输入的电平匹配问题
ADC3663的供电是1.8V,ADC3663的LVDS输出给到ZYNQ-7000的BANK12,BANK12的供电是2.5V的
下图是ZYNQ-7000的LVDS接口电平要求
下图是ADC3663的LVDS接口电平要求
目前的设计是串联电阻,串联电阻对Layout有些不友好
所以想请教一下当ADC3663的LVDS输出给到ZYNQ-7000的LVDS接收这两者之间可以直连吗?